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target/arm: Convert SHLL to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:19 -06:00 committed by Peter Maydell
parent 1fd9aa0b89
commit a05c56178a
2 changed files with 40 additions and 37 deletions
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2
target/arm/tcg/a64.decode
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@ -1685,3 +1685,5 @@ UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e
FCVTN_v 0.00 1110 0.1 00001 01101 0 ..... ..... @qrr_hs
FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s
BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
SHLL_v 0.10 1110 ..1 00001 00111 0 ..... ..... @qrr_e

75
target/arm/tcg/translate-a64.c
View File

@ -9113,6 +9113,43 @@ static ArithOneOp * const f_vector_bfcvtn[] = {
};
TRANS_FEAT(BFCVTN_v, aa64_bf16, do_2misc_narrow_vector, a, f_vector_bfcvtn)
static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
{
static NeonGenWidenFn * const widenfns[3] = {
gen_helper_neon_widen_u8,
gen_helper_neon_widen_u16,
tcg_gen_extu_i32_i64,
};
NeonGenWidenFn *widenfn;
TCGv_i64 tcg_res[2];
TCGv_i32 tcg_op;
int part, pass;
if (a->esz == MO_64) {
return false;
}
if (!fp_access_check(s)) {
return true;
}
tcg_op = tcg_temp_new_i32();
widenfn = widenfns[a->esz];
part = a->q ? 2 : 0;
for (pass = 0; pass < 2; pass++) {
read_vec_element_i32(s, tcg_op, a->rn, part + pass, MO_32);
tcg_res[pass] = tcg_temp_new_i64();
widenfn(tcg_res[pass], tcg_op);
tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << a->esz);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
}
return true;
}
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@ -9901,33 +9938,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
}
}
static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
{
/* Implement SHLL and SHLL2 */
int pass;
int part = is_q ? 2 : 0;
TCGv_i64 tcg_res[2];
for (pass = 0; pass < 2; pass++) {
static NeonGenWidenFn * const widenfns[3] = {
gen_helper_neon_widen_u8,
gen_helper_neon_widen_u16,
tcg_gen_extu_i32_i64,
};
NeonGenWidenFn *widenfn = widenfns[size];
TCGv_i32 tcg_op = tcg_temp_new_i32();
read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
tcg_res[pass] = tcg_temp_new_i64();
widenfn(tcg_res[pass], tcg_op);
tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
}
for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
}
}
/* AdvSIMD two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
@ -9948,16 +9958,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x13: /* SHLL, SHLL2 */
if (u == 0 || size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_shll(s, is_q, size, rn, rd);
return;
case 0xc ... 0xf:
case 0x16 ... 0x1f:
{
@ -10118,6 +10118,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x13: /* SHLL, SHLL2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
unallocated_encoding(s);
return;