SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

hw/riscv/sifive_e: Fix inheritance of SiFiveEState

Browse Source 
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
inherit from TYPE_MACHINE. This is an inconsistency which can cause
undefined behavior such as memory corruption.

Change SiFiveEState to inherit from MachineState since it is registered
as a machine.

Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220922075232.33653-1-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bernhard Beschow 2022-09-22 09:52:32 +02:00 committed by Alistair Francis
parent 9e37653b5c
commit 9dfa6c2aec
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/hw/riscv/sifive_e.h
View File

@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_cpu.h"
#include "hw/gpio/sifive_gpio.h" #include "hw/gpio/sifive_gpio.h"
#include "hw/boards.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \ #define RISCV_E_SOC(obj) \
@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
typedef struct SiFiveEState { typedef struct SiFiveEState {
/*< private >*/ /*< private >*/
SysBusDevice parent_obj; MachineState parent_obj;
/*< public >*/ /*< public >*/
SiFiveESoCState soc; SiFiveESoCState soc;