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target/xtensa: change SR number checks to assertions

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Opcode decoding with libisa takes care about range of valid group SRs,
like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr
implementations into assertions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2018-09-01 21:48:59 -07:00
parent 226444a844
commit 9dccbd1c69
1 changed files with 29 additions and 36 deletions
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27
target/xtensa/translate.c
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@ -634,38 +634,34 @@ static bool gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{ {
unsigned id = sr - IBREAKA; unsigned id = sr - IBREAKA;
if (id < dc->config->nibreak) {
TCGv_i32 tmp = tcg_const_i32(id); TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nibreak);
gen_helper_wsr_ibreaka(cpu_env, tmp, v); gen_helper_wsr_ibreaka(cpu_env, tmp, v);
tcg_temp_free(tmp); tcg_temp_free(tmp);
gen_jumpi_check_loop_end(dc, 0); gen_jumpi_check_loop_end(dc, 0);
return true; return true;
}
return false;
} }
static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{ {
unsigned id = sr - DBREAKA; unsigned id = sr - DBREAKA;
if (id < dc->config->ndbreak) {
TCGv_i32 tmp = tcg_const_i32(id); TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreaka(cpu_env, tmp, v); gen_helper_wsr_dbreaka(cpu_env, tmp, v);
tcg_temp_free(tmp); tcg_temp_free(tmp);
}
return false; return false;
} }
static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{ {
unsigned id = sr - DBREAKC; unsigned id = sr - DBREAKC;
if (id < dc->config->ndbreak) {
TCGv_i32 tmp = tcg_const_i32(id); TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->ndbreak);
gen_helper_wsr_dbreakc(cpu_env, tmp, v); gen_helper_wsr_dbreakc(cpu_env, tmp, v);
tcg_temp_free(tmp); tcg_temp_free(tmp);
}
return false; return false;
} }
@ -764,26 +760,23 @@ static bool gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{ {
uint32_t id = sr - CCOMPARE; uint32_t id = sr - CCOMPARE;
bool ret = false;
if (id < dc->config->nccompare) {
uint32_t int_bit = 1 << dc->config->timerint[id]; uint32_t int_bit = 1 << dc->config->timerint[id];
TCGv_i32 tmp = tcg_const_i32(id); TCGv_i32 tmp = tcg_const_i32(id);
assert(id < dc->config->nccompare);
tcg_gen_mov_i32(cpu_SR[sr], v); tcg_gen_mov_i32(cpu_SR[sr], v);
tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start(); gen_io_start();
} }
gen_helper_update_ccompare(cpu_env, tmp); gen_helper_update_ccompare(cpu_env, tmp);
tcg_temp_free(tmp);
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_end(); gen_io_end();
gen_jumpi_check_loop_end(dc, 0); gen_jumpi_check_loop_end(dc, 0);
ret = true; return true;
} }
tcg_temp_free(tmp); return false;
}
return ret;
} }
#else #else
static void gen_check_interrupts(DisasContext *dc) static void gen_check_interrupts(DisasContext *dc)