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target/arm: Introduce gen_exception_insn_el_v

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Create a function below gen_exception_insn that takes
the target_el as a TCGv_i32, replacing gen_exception_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-10 14:32:32 +01:00 committed by Peter Maydell
parent d3c5d50a5c
commit 9c9d03f0c5
1 changed files with 12 additions and 15 deletions
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27
target/arm/translate.c
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@ -1086,8 +1086,8 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
uint32_t syn, uint32_t target_el) uint32_t syn, TCGv_i32 tcg_el)
{ {
if (s->aarch64) { if (s->aarch64) {
gen_a64_set_pc_im(pc); gen_a64_set_pc_im(pc);
@ -1095,10 +1095,17 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
gen_set_condexec(s); gen_set_condexec(s);
gen_set_pc_im(s, pc); gen_set_pc_im(s, pc);
} }
gen_exception(excp, syn, target_el); gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
tcg_constant_i32(syn), tcg_el);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
uint32_t syn, uint32_t target_el)
{
gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
}
static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
{ {
gen_set_condexec(s); gen_set_condexec(s);
@ -1114,17 +1121,6 @@ void unallocated_encoding(DisasContext *s)
default_exception_el(s)); default_exception_el(s));
} }
static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
TCGv_i32 tcg_el)
{
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
gen_helper_exception_with_syndrome_el(cpu_env,
tcg_constant_i32(excp),
tcg_constant_i32(syn), tcg_el);
s->base.is_jmp = DISAS_NORETURN;
}
/* Force a TB lookup after an instruction that changes the CPU state. */ /* Force a TB lookup after an instruction that changes the CPU state. */
void gen_lookup_tb(DisasContext *s) void gen_lookup_tb(DisasContext *s)
{ {
@ -2847,7 +2843,8 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
tcg_el = tcg_constant_i32(3); tcg_el = tcg_constant_i32(3);
} }
gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF,
syn_uncategorized(), tcg_el);
tcg_temp_free_i32(tcg_el); tcg_temp_free_i32(tcg_el);
return false; return false;
} }