SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target/i386: do not use s->tmp0 for jumps on ECX ==/!= 0

Browse Source 
Create a new temporary, to ease the register allocator's work.

Creation of the temporary is pushed into gen_ext_tl, which
also allows NULL as the first parameter now.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2023-10-23 10:21:20 +02:00
parent 1ec46bf237
commit 9a5922d6bd
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target/i386/tcg/translate.c
View File

@ -720,6 +720,9 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign)
if (size == MO_TL) { if (size == MO_TL) {
return src; return src;
} }
if (!dst) {
dst = tcg_temp_new();
}
tcg_gen_ext_tl(dst, src, size | (sign ? MO_SIGN : 0)); tcg_gen_ext_tl(dst, src, size | (sign ? MO_SIGN : 0));
return dst; return dst;
} }
@ -736,9 +739,9 @@ static void gen_exts(MemOp ot, TCGv reg)
static void gen_op_j_ecx(DisasContext *s, TCGCond cond, TCGLabel *label1) static void gen_op_j_ecx(DisasContext *s, TCGCond cond, TCGLabel *label1)
{ {
tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]); TCGv tmp = gen_ext_tl(NULL, cpu_regs[R_ECX], s->aflag, false);
gen_extu(s->aflag, s->tmp0);
tcg_gen_brcondi_tl(cond, s->tmp0, 0, label1); tcg_gen_brcondi_tl(cond, tmp, 0, label1);
} }
static inline void gen_op_jz_ecx(DisasContext *s, TCGLabel *label1) static inline void gen_op_jz_ecx(DisasContext *s, TCGLabel *label1)