target/arm: Split m-nocp trans functions into their own file
Currently the trans functions for m-nocp.decode all live in translate-vfp.inc.c; move them out into their own translation unit, translate-m-nocp.c. The trans_* functions here are pure code motion with no changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210430132740.10391-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
5ce389f2e7
commit
9a5071abbc
@ -5,7 +5,7 @@ gen = [
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decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'),
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decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'),
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decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'),
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decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'),
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decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'),
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decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'),
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decodetree.process('m-nocp.decode', extra_args: '--static-decode=disas_m_nocp'),
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decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
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decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
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decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
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decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
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decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
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decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
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decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
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@ -26,6 +26,7 @@ arm_ss.add(files(
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'op_helper.c',
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'op_helper.c',
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'tlb_helper.c',
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'tlb_helper.c',
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'translate.c',
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'translate.c',
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'translate-m-nocp.c',
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'vec_helper.c',
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'vec_helper.c',
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'vfp_helper.c',
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'vfp_helper.c',
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'cpu_tcg.c',
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'cpu_tcg.c',
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@ -20,6 +20,9 @@
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#ifndef TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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#define TARGET_ARM_TRANSLATE_A64_H
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/* Prototypes for autogenerated disassembler functions */
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bool disas_m_nocp(DisasContext *dc, uint32_t insn);
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void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
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void load_reg_var(DisasContext *s, TCGv_i32 var, int reg);
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void arm_gen_condlabel(DisasContext *s);
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void arm_gen_condlabel(DisasContext *s);
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bool vfp_access_check(DisasContext *s);
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bool vfp_access_check(DisasContext *s);
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221
target/arm/translate-m-nocp.c
Normal file
221
target/arm/translate-m-nocp.c
Normal file
@ -0,0 +1,221 @@
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/*
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* ARM translation: M-profile NOCP special-case instructions
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*
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* Copyright (c) 2020 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "translate.h"
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#include "translate-a32.h"
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#include "decode-m-nocp.c.inc"
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/*
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* Decode VLLDM and VLSTM are nonstandard because:
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* * if there is no FPU then these insns must NOP in
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* Secure state and UNDEF in Nonsecure state
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* * if there is an FPU then these insns do not have
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* the usual behaviour that vfp_access_check() provides of
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* being controlled by CPACR/NSACR enable bits or the
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* lazy-stacking logic.
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*/
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static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
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{
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TCGv_i32 fptr;
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if (!arm_dc_feature(s, ARM_FEATURE_M) ||
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!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return false;
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}
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if (a->op) {
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/*
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* T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
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* to take the IMPDEF option to make memory accesses to the stack
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* slots that correspond to the D16-D31 registers (discarding
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* read data and writing UNKNOWN values), so for us the T2
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* encoding behaves identically to the T1 encoding.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return false;
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}
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} else {
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/*
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* T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
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* This is currently architecturally impossible, but we add the
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* check to stay in line with the pseudocode. Note that we must
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* emit code for the UNDEF so it takes precedence over the NOCP.
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*/
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if (dc_isar_feature(aa32_simd_r32, s)) {
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unallocated_encoding(s);
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return true;
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}
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}
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/*
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* If not secure, UNDEF. We must emit code for this
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* rather than returning false so that this takes
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* precedence over the m-nocp.decode NOCP fallback.
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*/
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if (!s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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/* If no fpu, NOP. */
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if (!dc_isar_feature(aa32_vfp, s)) {
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return true;
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}
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fptr = load_reg(s, a->rn);
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if (a->l) {
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gen_helper_v7m_vlldm(cpu_env, fptr);
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} else {
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gen_helper_v7m_vlstm(cpu_env, fptr);
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}
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tcg_temp_free_i32(fptr);
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/* End the TB, because we have updated FP control bits */
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s->base.is_jmp = DISAS_UPDATE_EXIT;
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return true;
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}
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static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
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{
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int btmreg, topreg;
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TCGv_i64 zero;
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TCGv_i32 aspen, sfpa;
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if (!dc_isar_feature(aa32_m_sec_state, s)) {
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/* Before v8.1M, fall through in decode to NOCP check */
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return false;
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}
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/* Explicitly UNDEF because this takes precedence over NOCP */
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if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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if (!dc_isar_feature(aa32_vfp_simd, s)) {
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/* NOP if we have neither FP nor MVE */
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return true;
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}
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/*
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* If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
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* active floating point context so we must NOP (without doing
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* any lazy state preservation or the NOCP check).
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*/
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aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
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sfpa = load_cpu_field(v7m.control[M_REG_S]);
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tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
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tcg_gen_or_i32(sfpa, sfpa, aspen);
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arm_gen_condlabel(s);
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tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
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if (s->fp_excp_el != 0) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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return true;
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}
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topreg = a->vd + a->imm - 1;
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btmreg = a->vd;
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/* Convert to Sreg numbers if the insn specified in Dregs */
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if (a->size == 3) {
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topreg = topreg * 2 + 1;
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btmreg *= 2;
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}
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if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
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/* UNPREDICTABLE: we choose to undef */
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unallocated_encoding(s);
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return true;
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}
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/* Silently ignore requests to clear D16-D31 if they don't exist */
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if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
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topreg = 31;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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/* Zero the Sregs from btmreg to topreg inclusive. */
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zero = tcg_const_i64(0);
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if (btmreg & 1) {
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write_neon_element64(zero, btmreg >> 1, 1, MO_32);
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btmreg++;
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}
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for (; btmreg + 1 <= topreg; btmreg += 2) {
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write_neon_element64(zero, btmreg >> 1, 0, MO_64);
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}
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if (btmreg == topreg) {
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write_neon_element64(zero, btmreg >> 1, 0, MO_32);
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btmreg++;
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}
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assert(btmreg == topreg + 1);
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/* TODO: when MVE is implemented, zero VPR here */
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return true;
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}
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static bool trans_NOCP(DisasContext *s, arg_nocp *a)
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{
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/*
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* Handle M-profile early check for disabled coprocessor:
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* all we need to do here is emit the NOCP exception if
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* the coprocessor is disabled. Otherwise we return false
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* and the real VFP/etc decode will handle the insn.
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*/
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assert(arm_dc_feature(s, ARM_FEATURE_M));
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if (a->cp == 11) {
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a->cp = 10;
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}
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if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
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(a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
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/* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
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a->cp = 10;
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}
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if (a->cp != 10) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), default_exception_el(s));
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return true;
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}
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if (s->fp_excp_el != 0) {
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gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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return true;
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}
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return false;
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}
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static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
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{
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/* This range needs a coprocessor check for v8.1M and later only */
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return false;
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}
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return trans_NOCP(s, a);
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}
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@ -3800,202 +3800,6 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
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return true;
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return true;
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}
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}
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/*
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* Decode VLLDM and VLSTM are nonstandard because:
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* * if there is no FPU then these insns must NOP in
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* Secure state and UNDEF in Nonsecure state
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* * if there is an FPU then these insns do not have
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* the usual behaviour that vfp_access_check() provides of
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* being controlled by CPACR/NSACR enable bits or the
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* lazy-stacking logic.
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*/
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static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
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{
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TCGv_i32 fptr;
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if (!arm_dc_feature(s, ARM_FEATURE_M) ||
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!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return false;
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}
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if (a->op) {
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/*
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* T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
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* to take the IMPDEF option to make memory accesses to the stack
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* slots that correspond to the D16-D31 registers (discarding
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* read data and writing UNKNOWN values), so for us the T2
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* encoding behaves identically to the T1 encoding.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return false;
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}
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} else {
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/*
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* T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
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* This is currently architecturally impossible, but we add the
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* check to stay in line with the pseudocode. Note that we must
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* emit code for the UNDEF so it takes precedence over the NOCP.
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*/
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if (dc_isar_feature(aa32_simd_r32, s)) {
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unallocated_encoding(s);
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return true;
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}
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}
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/*
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* If not secure, UNDEF. We must emit code for this
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* rather than returning false so that this takes
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* precedence over the m-nocp.decode NOCP fallback.
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*/
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if (!s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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/* If no fpu, NOP. */
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if (!dc_isar_feature(aa32_vfp, s)) {
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return true;
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}
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fptr = load_reg(s, a->rn);
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if (a->l) {
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gen_helper_v7m_vlldm(cpu_env, fptr);
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} else {
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gen_helper_v7m_vlstm(cpu_env, fptr);
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}
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tcg_temp_free_i32(fptr);
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/* End the TB, because we have updated FP control bits */
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s->base.is_jmp = DISAS_UPDATE_EXIT;
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return true;
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}
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static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
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{
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int btmreg, topreg;
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TCGv_i64 zero;
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TCGv_i32 aspen, sfpa;
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if (!dc_isar_feature(aa32_m_sec_state, s)) {
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/* Before v8.1M, fall through in decode to NOCP check */
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return false;
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}
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/* Explicitly UNDEF because this takes precedence over NOCP */
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if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
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unallocated_encoding(s);
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||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!dc_isar_feature(aa32_vfp_simd, s)) {
|
|
||||||
/* NOP if we have neither FP nor MVE */
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
|
|
||||||
* active floating point context so we must NOP (without doing
|
|
||||||
* any lazy state preservation or the NOCP check).
|
|
||||||
*/
|
|
||||||
aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
|
|
||||||
sfpa = load_cpu_field(v7m.control[M_REG_S]);
|
|
||||||
tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
|
|
||||||
tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
|
|
||||||
tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
|
|
||||||
tcg_gen_or_i32(sfpa, sfpa, aspen);
|
|
||||||
arm_gen_condlabel(s);
|
|
||||||
tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
|
|
||||||
|
|
||||||
if (s->fp_excp_el != 0) {
|
|
||||||
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
|
|
||||||
syn_uncategorized(), s->fp_excp_el);
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
topreg = a->vd + a->imm - 1;
|
|
||||||
btmreg = a->vd;
|
|
||||||
|
|
||||||
/* Convert to Sreg numbers if the insn specified in Dregs */
|
|
||||||
if (a->size == 3) {
|
|
||||||
topreg = topreg * 2 + 1;
|
|
||||||
btmreg *= 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
|
|
||||||
/* UNPREDICTABLE: we choose to undef */
|
|
||||||
unallocated_encoding(s);
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Silently ignore requests to clear D16-D31 if they don't exist */
|
|
||||||
if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
|
|
||||||
topreg = 31;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!vfp_access_check(s)) {
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Zero the Sregs from btmreg to topreg inclusive. */
|
|
||||||
zero = tcg_const_i64(0);
|
|
||||||
if (btmreg & 1) {
|
|
||||||
write_neon_element64(zero, btmreg >> 1, 1, MO_32);
|
|
||||||
btmreg++;
|
|
||||||
}
|
|
||||||
for (; btmreg + 1 <= topreg; btmreg += 2) {
|
|
||||||
write_neon_element64(zero, btmreg >> 1, 0, MO_64);
|
|
||||||
}
|
|
||||||
if (btmreg == topreg) {
|
|
||||||
write_neon_element64(zero, btmreg >> 1, 0, MO_32);
|
|
||||||
btmreg++;
|
|
||||||
}
|
|
||||||
assert(btmreg == topreg + 1);
|
|
||||||
/* TODO: when MVE is implemented, zero VPR here */
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool trans_NOCP(DisasContext *s, arg_nocp *a)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Handle M-profile early check for disabled coprocessor:
|
|
||||||
* all we need to do here is emit the NOCP exception if
|
|
||||||
* the coprocessor is disabled. Otherwise we return false
|
|
||||||
* and the real VFP/etc decode will handle the insn.
|
|
||||||
*/
|
|
||||||
assert(arm_dc_feature(s, ARM_FEATURE_M));
|
|
||||||
|
|
||||||
if (a->cp == 11) {
|
|
||||||
a->cp = 10;
|
|
||||||
}
|
|
||||||
if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
|
|
||||||
(a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
|
|
||||||
/* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
|
|
||||||
a->cp = 10;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (a->cp != 10) {
|
|
||||||
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
|
|
||||||
syn_uncategorized(), default_exception_el(s));
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (s->fp_excp_el != 0) {
|
|
||||||
gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
|
|
||||||
syn_uncategorized(), s->fp_excp_el);
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
|
|
||||||
{
|
|
||||||
/* This range needs a coprocessor check for v8.1M and later only */
|
|
||||||
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
return trans_NOCP(s, a);
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool trans_VINS(DisasContext *s, arg_VINS *a)
|
static bool trans_VINS(DisasContext *s, arg_VINS *a)
|
||||||
{
|
{
|
||||||
TCGv_i32 rd, rm;
|
TCGv_i32 rd, rm;
|
||||||
|
|||||||
@ -1273,7 +1273,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
|
|||||||
#define ARM_CP_RW_BIT (1 << 20)
|
#define ARM_CP_RW_BIT (1 << 20)
|
||||||
|
|
||||||
/* Include the VFP and Neon decoders */
|
/* Include the VFP and Neon decoders */
|
||||||
#include "decode-m-nocp.c.inc"
|
|
||||||
#include "translate-vfp.c.inc"
|
#include "translate-vfp.c.inc"
|
||||||
#include "translate-neon.c.inc"
|
#include "translate-neon.c.inc"
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user