target/hppa: Implement TCGCPUOps.tlb_fill_align
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order. Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339 Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -226,7 +226,7 @@ static const TCGCPUOps hppa_tcg_ops = {
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.restore_state_to_opc = hppa_restore_state_to_opc,
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.restore_state_to_opc = hppa_restore_state_to_opc,
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = hppa_cpu_tlb_fill,
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.tlb_fill_align = hppa_cpu_tlb_fill_align,
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.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
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.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
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.cpu_exec_halt = hppa_cpu_has_work,
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.cpu_exec_halt = hppa_cpu_has_work,
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.do_interrupt = hppa_cpu_do_interrupt,
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.do_interrupt = hppa_cpu_do_interrupt,
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@ -363,9 +363,9 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
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void hppa_ptlbe(CPUHPPAState *env);
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void hppa_ptlbe(CPUHPPAState *env);
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);
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void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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MemOp memop, int size, bool probe, uintptr_t ra);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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@ -424,12 +424,11 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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}
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}
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}
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}
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bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,
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MMUAccessType type, int mmu_idx,
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MMUAccessType type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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MemOp memop, int size, bool probe, uintptr_t ra)
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{
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = cpu_env(cs);
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CPUHPPAState *env = &cpu->env;
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int prot, excp, a_prot;
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int prot, excp, a_prot;
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hwaddr phys;
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hwaddr phys;
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@ -445,7 +444,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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break;
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break;
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}
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}
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excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, 0,
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excp = hppa_get_physical_address(env, addr, mmu_idx, a_prot, memop,
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&phys, &prot);
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&phys, &prot);
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if (unlikely(excp >= 0)) {
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if (unlikely(excp >= 0)) {
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if (probe) {
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if (probe) {
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@ -454,7 +453,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
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trace_hppa_tlb_fill_excp(env, addr, size, type, mmu_idx);
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/* Failure. Raise the indicated exception. */
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/* Failure. Raise the indicated exception. */
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raise_exception_with_ior(env, excp, retaddr, addr,
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raise_exception_with_ior(env, excp, ra, addr,
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MMU_IDX_MMU_DISABLED(mmu_idx));
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MMU_IDX_MMU_DISABLED(mmu_idx));
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}
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}
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@ -468,8 +467,12 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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* the large page protection mask. We do not require this,
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* the large page protection mask. We do not require this,
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* because we record the large page here in the hppa tlb.
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* because we record the large page here in the hppa tlb.
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*/
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*/
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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memset(out, 0, sizeof(*out));
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prot, mmu_idx, TARGET_PAGE_SIZE);
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out->phys_addr = phys;
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out->prot = prot;
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out->attrs = MEMTXATTRS_UNSPECIFIED;
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out->lg_page_size = TARGET_PAGE_BITS;
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return true;
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return true;
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}
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}
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