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Generic CPUs / accelerators patch queue

Browse Source 
- Merge "qemu/clang-tsa.h" within "qemu/compiler.h"
 - Various cleanups around accelerators initialization code
   (better user/system split)
 - Various trivial cleanups in accel/tcg/,
   Guard few TCG calls with tcg_enabled()
 - Explicit disassemble_info endianness
 - Improve dual-endianness support for MicroBlaze
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Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging

Generic CPUs / accelerators patch queue

- Merge "qemu/clang-tsa.h" within "qemu/compiler.h"
- Various cleanups around accelerators initialization code
  (better user/system split)
- Various trivial cleanups in accel/tcg/,
  Guard few TCG calls with tcg_enabled()
- Explicit disassemble_info endianness
- Improve dual-endianness support for MicroBlaze

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# gpg: Signature made Thu 06 Mar 2025 23:46:23 HKT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
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* tag 'accel-cpus-20250306' of https://github.com/philmd/qemu: (54 commits)
  include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition
  system: Open-code qemu_init_arch_modules() using target_name()
  target/i386: Mark WHPX APIC region as little-endian
  target/alpha: Do not mix exception flags and FPCR bits
  target/riscv: Convert misa_mxl_max using GLib macros
  target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
  target/xtensa: Finalize config in xtensa_register_core()
  target/sparc: Constify SPARCCPUClass::cpu_def
  target/i386: Constify X86CPUModel uses
  disas: Remove target_words_bigendian() call in initialize_debug_target()
  target/xtensa: Set disassemble_info::endian value in disas_set_info()
  target/sh4: Set disassemble_info::endian value in disas_set_info()
  target/riscv: Set disassemble_info::endian value in disas_set_info()
  target/ppc: Set disassemble_info::endian value in disas_set_info()
  target/mips: Set disassemble_info::endian value in disas_set_info()
  target/microblaze: Set disassemble_info::endian value in disas_set_info
  target/arm: Set disassemble_info::endian value in disas_set_info()
  target: Set disassemble_info::endian value for big-endian targets
  target: Set disassemble_info::endian value for little-endian targets
  target/mips: Fix possible MSA int overflow
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-03-07 07:39:49 +08:00
commit 98c7362b1e
110 changed files with 544 additions and 533 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -175,7 +175,7 @@ F: include/exec/helper-info.c.inc
F: include/exec/page-protection.h
F: include/system/cpus.h
F: include/system/tcg.h
F: include/hw/core/tcg-cpu-ops.h
F: include/accel/tcg/cpu-ops.h
F: host/include/*/host/cpuinfo.h
F: util/cpuinfo-*.c
F: include/tcg/
@ -499,7 +499,7 @@ R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: include/qemu/accel.h
F: include/system/accel-*.h
F: include/hw/core/accel-cpu.h
F: include/accel/accel-cpu-target.h
F: accel/accel-*.c
F: accel/Makefile.objs
F: accel/stubs/Makefile.objs
@ -3798,6 +3798,7 @@ Overall usermode emulation
M: Riku Voipio <riku.voipio@iki.fi>
S: Maintained
F: accel/tcg/user-exec*.c
F: hw/core/cpu-user.c
F: include/user/
F: common-user/

1
accel/accel-system.c
View File

@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu/accel.h"
#include "hw/boards.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/error-report.h"
#include "accel-system.h"

3
accel/accel-target.c
View File

@ -27,7 +27,7 @@
#include "qemu/accel.h"
#include "cpu.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#ifndef CONFIG_USER_ONLY
#include "accel-system.h"
@ -38,6 +38,7 @@ static const TypeInfo accel_type = {
.parent = TYPE_OBJECT,
.class_size = sizeof(AccelClass),
.instance_size = sizeof(AccelState),
.abstract = true,
};
/* Lookup AccelClass from opt_name. Returns NULL if not found */

1
accel/hvf/hvf-accel-ops.c
View File

@ -54,6 +54,7 @@
#include "exec/exec-all.h"
#include "gdbstub/enums.h"
#include "hw/boards.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/hvf.h"
#include "system/hvf_int.h"

1
accel/kvm/kvm-accel-ops.c
View File

@ -16,6 +16,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "system/accel-ops.h"
#include "system/kvm.h"
#include "system/kvm_int.h"
#include "system/runstate.h"

2
accel/kvm/kvm-cpus.h
View File

@ -10,8 +10,6 @@
#ifndef KVM_CPUS_H
#define KVM_CPUS_H
#include "system/cpus.h"
int kvm_init_vcpu(CPUState *cpu, Error **errp);
int kvm_cpu_exec(CPUState *cpu);
void kvm_destroy_vcpu(CPUState *cpu);

1
accel/qtest/qtest.c
View File

@ -18,6 +18,7 @@
#include "qemu/option.h"
#include "qemu/config-file.h"
#include "qemu/accel.h"
#include "system/accel-ops.h"
#include "system/qtest.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"

4
accel/stubs/tcg-stub.c
View File

@ -14,10 +14,6 @@
#include "exec/tb-flush.h"
#include "exec/exec-all.h"
void tb_flush(CPUState *cpu)
{
}
G_NORETURN void cpu_loop_exit(CPUState *cpu)
{
g_assert_not_reached();

34
accel/tcg/cpu-exec-common.c
View File

@ -18,13 +18,45 @@
*/
#include "qemu/osdep.h"
#include "system/cpus.h"
#include "exec/log.h"
#include "system/tcg.h"
#include "qemu/plugin.h"
#include "internal-common.h"
bool tcg_allowed;
bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
{
return cpu->tcg_cflags & flags;
}
void tcg_cflags_set(CPUState *cpu, uint32_t flags)
{
cpu->tcg_cflags |= flags;
}
uint32_t curr_cflags(CPUState *cpu)
{
uint32_t cflags = cpu->tcg_cflags;
/*
* Record gdb single-step. We should be exiting the TB by raising
* EXCP_DEBUG, but to simplify other tests, disable chaining too.
*
* For singlestep and -d nochain, suppress goto_tb so that
* we can log -d cpu,exec after every TB.
*/
if (unlikely(cpu->singlestep_enabled)) {
cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
} else if (qatomic_read(&one_insn_per_tb)) {
cflags |= CF_NO_GOTO_TB | 1;
} else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
cflags |= CF_NO_GOTO_TB;
}
return cflags;
}
/* exit the current TB, but without causing any exception to be raised */
void cpu_loop_exit_noexc(CPUState *cpu)
{

35
accel/tcg/cpu-exec.c
View File

@ -22,7 +22,7 @@
#include "qapi/error.h"
#include "qapi/type-helpers.h"
#include "hw/core/cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "trace.h"
#include "disas/disas.h"
#include "exec/cpu-common.h"
@ -33,7 +33,6 @@
#include "qemu/rcu.h"
#include "exec/log.h"
#include "qemu/main-loop.h"
#include "system/cpus.h"
#include "exec/cpu-all.h"
#include "system/cpu-timers.h"
#include "exec/replay-core.h"
@ -148,38 +147,6 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
}
#endif /* CONFIG USER ONLY */
bool tcg_cflags_has(CPUState *cpu, uint32_t flags)
{
return cpu->tcg_cflags & flags;
}
void tcg_cflags_set(CPUState *cpu, uint32_t flags)
{
cpu->tcg_cflags |= flags;
}
uint32_t curr_cflags(CPUState *cpu)
{
uint32_t cflags = cpu->tcg_cflags;
/*
* Record gdb single-step. We should be exiting the TB by raising
* EXCP_DEBUG, but to simplify other tests, disable chaining too.
*
* For singlestep and -d nochain, suppress goto_tb so that
* we can log -d cpu,exec after every TB.
*/
if (unlikely(cpu->singlestep_enabled)) {
cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
} else if (qatomic_read(&one_insn_per_tb)) {
cflags |= CF_NO_GOTO_TB | 1;
} else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
cflags |= CF_NO_GOTO_TB;
}
return cflags;
}
struct tb_desc {
vaddr pc;
uint64_t cs_base;

2
accel/tcg/cputlb.c
View File

@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/memory.h"

2
accel/tcg/icount-common.c
View File

@ -48,6 +48,8 @@ static bool icount_sleep = true;
/* Arbitrarily pick 1MIPS as the minimum allowable speed. */
#define MAX_ICOUNT_SHIFT 10
bool icount_align_option;
/* Do not count executed instructions */
ICountMode use_icount = ICOUNT_DISABLED;

13
accel/tcg/internal-common.h
View File

@ -17,6 +17,8 @@ extern int64_t max_advance;
extern bool one_insn_per_tb;
extern bool icount_align_option;
/*
* Return true if CS is not running in parallel with other cpus, either
* because there are no other cpus or we are within an exclusive context.
@ -53,6 +55,17 @@ TranslationBlock *tb_link_page(TranslationBlock *tb);
void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t host_pc);
/**
* tlb_init - initialize a CPU's TLB
* @cpu: CPU whose TLB should be initialized
*/
void tlb_init(CPUState *cpu);
/**
* tlb_destroy - destroy a CPU's TLB
* @cpu: CPU whose TLB should be destroyed
*/
void tlb_destroy(CPUState *cpu);
bool tcg_exec_realizefn(CPUState *cpu, Error **errp);
void tcg_exec_unrealizefn(CPUState *cpu);

1
accel/tcg/monitor.c
View File

@ -13,7 +13,6 @@
#include "qapi/type-helpers.h"
#include "qapi/qapi-commands-machine.h"
#include "monitor/monitor.h"
#include "system/cpus.h"
#include "system/cpu-timers.h"
#include "system/tcg.h"
#include "tcg/tcg.h"

1
accel/tcg/tcg-accel-ops.c
View File

@ -26,6 +26,7 @@
*/
#include "qemu/osdep.h"
#include "system/accel-ops.h"
#include "system/tcg.h"
#include "system/replay.h"
#include "system/cpu-timers.h"

3
accel/tcg/translate-all.c
View File

@ -54,11 +54,10 @@
#include "qemu/cacheinfo.h"
#include "qemu/timer.h"
#include "exec/log.h"
#include "system/cpus.h"
#include "system/cpu-timers.h"
#include "system/tcg.h"
#include "qapi/error.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "tb-jmp-cache.h"
#include "tb-hash.h"
#include "tb-context.h"

11
accel/tcg/user-exec-stub.c
View File

@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "hw/core/cpu.h"
#include "exec/replay-core.h"
#include "internal-common.h"
void cpu_resume(CPUState *cpu)
{
@ -18,6 +19,16 @@ void cpu_exec_reset_hold(CPUState *cpu)
{
}
/* User mode emulation does not support softmmu yet. */
void tlb_init(CPUState *cpu)
{
}
void tlb_destroy(CPUState *cpu)
{
}
/* User mode emulation does not support record/replay yet. */
bool replay_exception(void)

84
accel/tcg/user-exec.c
View File

@ -17,8 +17,9 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "disas/disas.h"
#include "exec/vaddr.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "qemu/bitops.h"
@ -30,6 +31,8 @@
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "qemu/bswap.h"
#include "qemu/int128.h"
#include "trace.h"
#include "tcg/tcg-ldst.h"
#include "internal-common.h"
@ -969,6 +972,85 @@ static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr,
return ret;
}
/* physical memory access (slow version, mainly for debug) */
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void *ptr, size_t len, bool is_write)
{
int flags;
vaddr l, page;
uint8_t *buf = ptr;
ssize_t written;
int ret = -1;
int fd = -1;
mmap_lock();
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len) {
l = len;
}
flags = page_get_flags(page);
if (!(flags & PAGE_VALID)) {
goto out_close;
}
if (is_write) {
if (flags & PAGE_WRITE) {
memcpy(g2h(cpu, addr), buf, l);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
fd = open("/proc/self/mem", O_WRONLY);
if (fd == -1) {
goto out;
}
}
/*
* If there is a TranslationBlock and we weren't bypassing the
* host page protection, the memcpy() above would SEGV,
* ultimately leading to page_unprotect(). So invalidate the
* translations manually. Both invalidation and pwrite() must
* be under mmap_lock() in order to prevent the creation of
* another TranslationBlock in between.
*/
tb_invalidate_phys_range(addr, addr + l - 1);
written = pwrite(fd, buf, l,
(off_t)(uintptr_t)g2h_untagged(addr));
if (written != l) {
goto out_close;
}
}
} else if (flags & PAGE_READ) {
memcpy(buf, g2h(cpu, addr), l);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
fd = open("/proc/self/mem", O_RDONLY);
if (fd == -1) {
goto out;
}
}
if (pread(fd, buf, l,
(off_t)(uintptr_t)g2h_untagged(addr)) != l) {
goto out_close;
}
}
len -= l;
buf += l;
addr += l;
}
ret = 0;
out_close:
if (fd != -1) {
close(fd);
}
out:
mmap_unlock();
return ret;
}
#include "ldst_atomicity.c.inc"
static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,

2
accel/tcg/watchpoint.c
View File

@ -26,7 +26,7 @@
#include "tb-internal.h"
#include "system/tcg.h"
#include "system/replay.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "hw/core/cpu.h"
#include "internal-common.h"

1
accel/xen/xen-all.c
View File

@ -18,6 +18,7 @@
#include "hw/xen/xen_igd.h"
#include "chardev/char.h"
#include "qemu/accel.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/xen.h"
#include "system/runstate.h"

1
block/create.c
View File

@ -24,7 +24,6 @@
#include "qemu/osdep.h"
#include "block/block_int.h"
#include "qemu/clang-tsa.h"
#include "qemu/job.h"
#include "qemu/main-loop.h"
#include "qapi/qapi-commands-block-core.h"

1
bsd-user/qemu.h
View File

@ -40,7 +40,6 @@ extern char **environ;
#include "target.h"
#include "exec/gdbstub.h"
#include "exec/page-protection.h"
#include "qemu/clang-tsa.h"
#include "accel/tcg/vcpu-state.h"
#include "qemu-os.h"

2
bsd-user/signal.c
View File

@ -29,7 +29,7 @@
#include "gdbstub/user.h"
#include "signal-common.h"
#include "trace.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "host-signal.h"
/* target_siginfo_t must fit in gdbstub's siginfo save area. */

1
cpu-common.c
View File

@ -21,7 +21,6 @@
#include "qemu/main-loop.h"
#include "exec/cpu-common.h"
#include "hw/core/cpu.h"
#include "system/cpus.h"
#include "qemu/lockable.h"
#include "trace/trace-root.h"

205
cpu-target.c
View File

@ -19,22 +19,13 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "exec/target_page.h"
#include "exec/page-protection.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "migration/vmstate.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#include "user/page-protection.h"
#else
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
#endif
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/tcg.h"
#include "exec/tswap.h"
@ -42,28 +33,34 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
#include "exec/translation-block.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
#include "hw/core/cpu.h"
#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
CPUState *cpu = opaque;
if (tcg_enabled()) {
CPUState *cpu = opaque;
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
version_id is increased. */
cpu->interrupt_request &= ~0x01;
tlb_flush(cpu);
/*
* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
* version_id is increased.
*/
cpu->interrupt_request &= ~0x01;
/* loadvm has just updated the content of RAM, bypassing the
* usual mechanisms that ensure we flush TBs for writes to
* memory we've translated code from. So we must flush all TBs,
* which will now be stale.
*/
tb_flush(cpu);
tlb_flush(cpu);
/*
* loadvm has just updated the content of RAM, bypassing the
* usual mechanisms that ensure we flush TBs for writes to
* memory we've translated code from. So we must flush all TBs,
* which will now be stale.
*/
tb_flush(cpu);
}
return 0;
}
@ -134,9 +131,6 @@ const VMStateDescription vmstate_cpu_common = {
bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
if (!accel_cpu_common_realize(cpu, errp)) {
return false;
}
@ -180,72 +174,6 @@ void cpu_exec_unrealizefn(CPUState *cpu)
accel_cpu_common_unrealize(cpu);
}
/*
* This can't go in hw/core/cpu.c because that file is compiled only
* once for both user-mode and system builds.
*/
static const Property cpu_common_props[] = {
#ifdef CONFIG_USER_ONLY
/*
* Create a property for the user-only object, so users can
* adjust prctl(PR_SET_UNALIGN) from the command-line.
* Has no effect if the target does not support the feature.
*/
DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
prctl_unalign_sigbus, false),
#else
/*
* Create a memory property for system CPU object, so users can
* wire up its memory. The default if no link is set up is to use
* the system address space.
*/
DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
MemoryRegion *),
#endif
};
#ifndef CONFIG_USER_ONLY
static bool cpu_get_start_powered_off(Object *obj, Error **errp)
{
CPUState *cpu = CPU(obj);
return cpu->start_powered_off;
}
static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
{
CPUState *cpu = CPU(obj);
cpu->start_powered_off = value;
}
#endif
void cpu_class_init_props(DeviceClass *dc)
{
#ifndef CONFIG_USER_ONLY
ObjectClass *oc = OBJECT_CLASS(dc);
/*
* We can't use DEFINE_PROP_BOOL in the Property array for this
* property, because we want this to be settable after realize.
*/
object_class_property_add_bool(oc, "start-powered-off",
cpu_get_start_powered_off,
cpu_set_start_powered_off);
#endif
device_class_set_props(dc, cpu_common_props);
}
void cpu_exec_initfn(CPUState *cpu)
{
cpu->as = NULL;
cpu->num_ases = 0;
#ifndef CONFIG_USER_ONLY
cpu->memory = get_system_memory();
object_ref(OBJECT(cpu->memory));
#endif
}
char *cpu_model_from_type(const char *typename)
{
const char *suffix = "-" CPU_RESOLVING_TYPE;
@ -372,97 +300,6 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...)
abort();
}
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void *ptr, size_t len, bool is_write)
{
int flags;
vaddr l, page;
void * p;
uint8_t *buf = ptr;
ssize_t written;
int ret = -1;
int fd = -1;
while (len > 0) {
page = addr & TARGET_PAGE_MASK;
l = (page + TARGET_PAGE_SIZE) - addr;
if (l > len)
l = len;
flags = page_get_flags(page);
if (!(flags & PAGE_VALID)) {
goto out_close;
}
if (is_write) {
if (flags & PAGE_WRITE) {
/* XXX: this code should not depend on lock_user */
p = lock_user(VERIFY_WRITE, addr, l, 0);
if (!p) {
goto out_close;
}
memcpy(p, buf, l);
unlock_user(p, addr, l);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
fd = open("/proc/self/mem", O_WRONLY);
if (fd == -1) {
goto out;
}
}
/*
* If there is a TranslationBlock and we weren't bypassing the
* host page protection, the memcpy() above would SEGV,
* ultimately leading to page_unprotect(). So invalidate the
* translations manually. Both invalidation and pwrite() must
* be under mmap_lock() in order to prevent the creation of
* another TranslationBlock in between.
*/
mmap_lock();
tb_invalidate_phys_range(addr, addr + l - 1);
written = pwrite(fd, buf, l,
(off_t)(uintptr_t)g2h_untagged(addr));
mmap_unlock();
if (written != l) {
goto out_close;
}
}
} else if (flags & PAGE_READ) {
/* XXX: this code should not depend on lock_user */
p = lock_user(VERIFY_READ, addr, l, 1);
if (!p) {
goto out_close;
}
memcpy(buf, p, l);
unlock_user(p, addr, 0);
} else {
/* Bypass the host page protection using ptrace. */
if (fd == -1) {
fd = open("/proc/self/mem", O_RDONLY);
if (fd == -1) {
goto out;
}
}
if (pread(fd, buf, l,
(off_t)(uintptr_t)g2h_untagged(addr)) != l) {
goto out_close;
}
}
len -= l;
buf += l;
addr += l;
}
ret = 0;
out_close:
if (fd != -1) {
close(fd);
}
out:
return ret;
}
#endif
bool target_words_bigendian(void)
{
return TARGET_BIG_ENDIAN;

8
disas/disas-common.c
View File

@ -7,7 +7,6 @@
#include "disas/disas.h"
#include "disas/capstone.h"
#include "hw/core/cpu.h"
#include "exec/tswap.h"
#include "disas-internal.h"
@ -61,15 +60,12 @@ void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu)
s->cpu = cpu;
s->info.print_address_func = print_address;
if (target_words_bigendian()) {
s->info.endian = BFD_ENDIAN_BIG;
} else {
s->info.endian = BFD_ENDIAN_LITTLE;
}
s->info.endian = BFD_ENDIAN_UNKNOWN;
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->disas_set_info) {
cc->disas_set_info(cpu, &s->info);
g_assert(s->info.endian != BFD_ENDIAN_UNKNOWN);
}
}

6
gdbstub/system.c
View File

@ -19,9 +19,11 @@
#include "gdbstub/commands.h"
#include "exec/hwaddr.h"
#include "exec/tb-flush.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "system/runstate.h"
#include "system/replay.h"
#include "system/tcg.h"
#include "hw/core/cpu.h"
#include "hw/cpu/cluster.h"
#include "hw/boards.h"
@ -171,7 +173,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state)
} else {
trace_gdbstub_hit_break();
}
tb_flush(cpu);
if (tcg_enabled()) {
tb_flush(cpu);
}
ret = GDB_SIGNAL_TRAP;
break;
case RUN_STATE_PAUSED:

6
hw/core/cpu-common.c
View File

@ -238,13 +238,17 @@ static void cpu_common_initfn(Object *obj)
{
CPUState *cpu = CPU(obj);
/* cache the cpu class for the hotpath */
cpu->cc = CPU_GET_CLASS(cpu);
gdb_init_cpu(cpu);
cpu->cpu_index = UNASSIGNED_CPU_INDEX;
cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
cpu->as = NULL;
cpu->num_ases = 0;
/* user-mode doesn't have configurable SMP topology */
/* the default value is changed by qemu_init_vcpu() for system-mode */
cpu->nr_threads = 1;
cpu->cflags_next_tb = -1;
/* allocate storage for thread info, initialise condition variables */
cpu->thread = g_new0(QemuThread, 1);

47
hw/core/cpu-system.c
View File

@ -20,7 +20,11 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
#include "exec/tswap.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "hw/core/sysemu-cpu-ops.h"
bool cpu_paging_enabled(const CPUState *cpu)
@ -147,3 +151,46 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
}
return res;
}
static const Property cpu_system_props[] = {
/*
* Create a memory property for system CPU object, so users can
* wire up its memory. The default if no link is set up is to use
* the system address space.
*/
DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
MemoryRegion *),
};
static bool cpu_get_start_powered_off(Object *obj, Error **errp)
{
CPUState *cpu = CPU(obj);
return cpu->start_powered_off;
}
static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
{
CPUState *cpu = CPU(obj);
cpu->start_powered_off = value;
}
void cpu_class_init_props(DeviceClass *dc)
{
ObjectClass *oc = OBJECT_CLASS(dc);
/*
* We can't use DEFINE_PROP_BOOL in the Property array for this
* property, because we want this to be settable after realize.
*/
object_class_property_add_bool(oc, "start-powered-off",
cpu_get_start_powered_off,
cpu_set_start_powered_off);
device_class_set_props(dc, cpu_system_props);
}
void cpu_exec_initfn(CPUState *cpu)
{
cpu->memory = get_system_memory();
object_ref(OBJECT(cpu->memory));
}

32
hw/core/cpu-user.c Normal file
View File

@ -0,0 +1,32 @@
/*
* QEMU CPU model (user specific)
*
* Copyright (c) Linaro, Ltd.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
static const Property cpu_user_props[] = {
/*
* Create a property for the user-only object, so users can
* adjust prctl(PR_SET_UNALIGN) from the command-line.
* Has no effect if the target does not support the feature.
*/
DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
prctl_unalign_sigbus, false),
};
void cpu_class_init_props(DeviceClass *dc)
{
device_class_set_props(dc, cpu_user_props);
}
void cpu_exec_initfn(CPUState *cpu)
{
/* nothing to do */
}

5
hw/core/generic-loader.c
View File

@ -47,11 +47,8 @@ static void generic_loader_reset(void *opaque)
GenericLoaderState *s = GENERIC_LOADER(opaque);
if (s->set_pc) {
CPUClass *cc = CPU_GET_CLASS(s->cpu);
cpu_reset(s->cpu);
if (cc) {
cc->set_pc(s->cpu, s->addr);
}
cpu_set_pc(s->cpu, s->addr);
}
if (s->data_len) {

5
hw/core/meson.build
View File

@ -46,4 +46,7 @@ system_ss.add(files(
'vm-change-state-handler.c',
'clock-vmstate.c',
))
user_ss.add(files('qdev-user.c'))
user_ss.add(files(
'cpu-user.c',
'qdev-user.c',
))

2
hw/mips/jazz.c
View File

@ -50,7 +50,7 @@
#include "qemu/error-report.h"
#include "qemu/help_option.h"
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "cpu.h"

2
hw/openrisc/openrisc_sim.c
View File

@ -306,8 +306,6 @@ static void openrisc_sim_init(MachineState *machine)
exit(1);
}
cpu_openrisc_clock_init(cpus[n]);
qemu_register_reset(main_cpu_reset, cpus[n]);
}

2
hw/openrisc/virt.c
View File

@ -487,8 +487,6 @@ static void openrisc_virt_init(MachineState *machine)
exit(1);
}
cpu_openrisc_clock_init(cpus[n]);
qemu_register_reset(main_cpu_reset, cpus[n]);
}

7
include/hw/core/accel-cpu.h → include/accel/accel-cpu-target.h
View File

@ -8,8 +8,8 @@
* See the COPYING file in the top-level directory.
*/
#ifndef ACCEL_CPU_H
#define ACCEL_CPU_H
#ifndef ACCEL_CPU_TARGET_H
#define ACCEL_CPU_TARGET_H
/*
* This header is used to define new accelerator-specific target-specific
@ -20,6 +20,9 @@
* subclasses in target/, or the accel implementation itself in accel/
*/
#include "qom/object.h"
#include "cpu.h"
#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE
#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU)
typedef struct AccelCPUClass AccelCPUClass;

0
include/hw/core/tcg-cpu-ops.h → include/accel/tcg/cpu-ops.h
View File

1
include/block/block_int-common.h
View File

@ -28,7 +28,6 @@
#include "block/block-common.h"
#include "block/block-global-state.h"
#include "block/snapshot.h"
#include "qemu/clang-tsa.h"
#include "qemu/iov.h"
#include "qemu/rcu.h"
#include "qemu/stats64.h"

2
include/block/graph-lock.h
View File

@ -20,8 +20,6 @@
#ifndef GRAPH_LOCK_H
#define GRAPH_LOCK_H
#include "qemu/clang-tsa.h"
/**
* Graph Lock API
* This API provides a rwlock used to protect block layer

16
include/exec/exec-all.h
View File

@ -29,16 +29,6 @@
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
/**
* tlb_init - initialize a CPU's TLB
* @cpu: CPU whose TLB should be initialized
*/
void tlb_init(CPUState *cpu);
/**
* tlb_destroy - destroy a CPU's TLB
* @cpu: CPU whose TLB should be destroyed
*/
void tlb_destroy(CPUState *cpu);
/**
* tlb_flush_page:
* @cpu: CPU whose TLB should be flushed
@ -223,12 +213,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr,
hwaddr paddr, int prot,
int mmu_idx, vaddr size);
#else
static inline void tlb_init(CPUState *cpu)
{
}
static inline void tlb_destroy(CPUState *cpu)
{
}
static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
{
}

2
include/exec/page-protection.h
View File

@ -40,8 +40,6 @@
#ifdef CONFIG_USER_ONLY
#include "qemu/clang-tsa.h"
void TSA_NO_TSA mmap_lock(void);
void TSA_NO_TSA mmap_unlock(void);
bool have_mmap_lock(void);

1
include/exec/poison.h
View File

@ -48,6 +48,7 @@
#pragma GCC poison TARGET_PAGE_MASK
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB

6
include/hw/core/cpu.h
View File

@ -124,7 +124,9 @@ struct SysemuCPUOps;
* @get_pc: Callback for getting the Program Counter register.
* As above, with the semantics of the target architecture.
* @gdb_read_register: Callback for letting GDB read a register.
* No more than @gdb_num_core_regs registers can be read.
* @gdb_write_register: Callback for letting GDB write a register.
* No more than @gdb_num_core_regs registers can be written.
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
* breakpoint. Used by AVR to handle a gdb mis-feature with
* its Harvard architecture split code and data.
@ -614,6 +616,8 @@ extern bool mttcg_enabled;
*/
bool cpu_paging_enabled(const CPUState *cpu);
#if !defined(CONFIG_USER_ONLY)
/**
* cpu_get_memory_mapping:
* @cpu: The CPU whose memory mappings are to be obtained.
@ -625,8 +629,6 @@ bool cpu_paging_enabled(const CPUState *cpu);
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp);
#if !defined(CONFIG_USER_ONLY)
/**
* cpu_write_elf64_note:
* @f: pointer to a function that writes memory to a file

114
include/qemu/clang-tsa.h
View File

@ -1,114 +0,0 @@
#ifndef CLANG_TSA_H
#define CLANG_TSA_H
/*
* Copyright 2018 Jarkko Hietaniemi <jhi@iki.fi>
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without
* limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html
*
* TSA is available since clang 3.6-ish.
*/
#ifdef __clang__
# define TSA(x) __attribute__((x))
#else
# define TSA(x) /* No TSA, make TSA attributes no-ops. */
#endif
/* TSA_CAPABILITY() is used to annotate typedefs:
*
* typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex;
*/
#define TSA_CAPABILITY(x) TSA(capability(x))
/* TSA_GUARDED_BY() is used to annotate global variables,
* the data is guarded:
*
* Foo foo TSA_GUARDED_BY(mutex);
*/
#define TSA_GUARDED_BY(x) TSA(guarded_by(x))
/* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data
* behind the pointer is guarded.
*
* Foo* ptr TSA_PT_GUARDED_BY(mutex);
*/
#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x))
/* The TSA_REQUIRES() is used to annotate functions: the caller of the
* function MUST hold the resource, the function will NOT release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_REQUIRES(mutex);
*/
#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__))
#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__))
/* TSA_EXCLUDES() is used to annotate functions: the caller of the
* function MUST NOT hold resource, the function first acquires the
* resource, and then releases it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_EXCLUDES(mutex);
*/
#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__))
/* TSA_ACQUIRE() is used to annotate functions: the caller of the
* function MUST NOT hold the resource, the function will acquire the
* resource, but NOT release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_ACQUIRE(mutex);
*/
#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__))
#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__))
/* TSA_RELEASE() is used to annotate functions: the caller of the
* function MUST hold the resource, but the function will then release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_RELEASE(mutex);
*/
#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__))
#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__))
/* TSA_NO_TSA is used to annotate functions. Use only when you need to.
*
* void Foo(void) TSA_NO_TSA;
*/
#define TSA_NO_TSA TSA(no_thread_safety_analysis)
/*
* TSA_ASSERT() is used to annotate functions: This function will assert that
* the lock is held. When it returns, the caller of the function is assumed to
* already hold the resource.
*
* More than one mutex may be specified, comma-separated.
*/
#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__))
#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__))
#endif /* #ifndef CLANG_TSA_H */

96
include/qemu/compiler.h
View File

@ -207,6 +207,102 @@
# define QEMU_USED
#endif
/*
* http://clang.llvm.org/docs/ThreadSafetyAnalysis.html
*
* TSA is available since clang 3.6-ish.
*/
#ifdef __clang__
# define TSA(x) __attribute__((x))
#else
# define TSA(x) /* No TSA, make TSA attributes no-ops. */
#endif
/*
* TSA_CAPABILITY() is used to annotate typedefs:
*
* typedef pthread_mutex_t TSA_CAPABILITY("mutex") tsa_mutex;
*/
#define TSA_CAPABILITY(x) TSA(capability(x))
/*
* TSA_GUARDED_BY() is used to annotate global variables,
* the data is guarded:
*
* Foo foo TSA_GUARDED_BY(mutex);
*/
#define TSA_GUARDED_BY(x) TSA(guarded_by(x))
/*
* TSA_PT_GUARDED_BY() is used to annotate global pointers, the data
* behind the pointer is guarded.
*
* Foo* ptr TSA_PT_GUARDED_BY(mutex);
*/
#define TSA_PT_GUARDED_BY(x) TSA(pt_guarded_by(x))
/*
* The TSA_REQUIRES() is used to annotate functions: the caller of the
* function MUST hold the resource, the function will NOT release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_REQUIRES(mutex);
*/
#define TSA_REQUIRES(...) TSA(requires_capability(__VA_ARGS__))
#define TSA_REQUIRES_SHARED(...) TSA(requires_shared_capability(__VA_ARGS__))
/*
* TSA_EXCLUDES() is used to annotate functions: the caller of the
* function MUST NOT hold resource, the function first acquires the
* resource, and then releases it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_EXCLUDES(mutex);
*/
#define TSA_EXCLUDES(...) TSA(locks_excluded(__VA_ARGS__))
/*
* TSA_ACQUIRE() is used to annotate functions: the caller of the
* function MUST NOT hold the resource, the function will acquire the
* resource, but NOT release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_ACQUIRE(mutex);
*/
#define TSA_ACQUIRE(...) TSA(acquire_capability(__VA_ARGS__))
#define TSA_ACQUIRE_SHARED(...) TSA(acquire_shared_capability(__VA_ARGS__))
/*
* TSA_RELEASE() is used to annotate functions: the caller of the
* function MUST hold the resource, but the function will then release it.
*
* More than one mutex may be specified, comma-separated.
*
* void Foo(void) TSA_RELEASE(mutex);
*/
#define TSA_RELEASE(...) TSA(release_capability(__VA_ARGS__))
#define TSA_RELEASE_SHARED(...) TSA(release_shared_capability(__VA_ARGS__))
/*
* TSA_NO_TSA is used to annotate functions. Use only when you need to.
*
* void Foo(void) TSA_NO_TSA;
*/
#define TSA_NO_TSA TSA(no_thread_safety_analysis)
/*
* TSA_ASSERT() is used to annotate functions: This function will assert that
* the lock is held. When it returns, the caller of the function is assumed to
* already hold the resource.
*
* More than one mutex may be specified, comma-separated.
*/
#define TSA_ASSERT(...) TSA(assert_capability(__VA_ARGS__))
#define TSA_ASSERT_SHARED(...) TSA(assert_shared_capability(__VA_ARGS__))
/*
* Ugly CPP trick that is like "defined FOO", but also works in C
* code. Useful to replace #ifdef with "if" statements; assumes

1
include/qemu/thread.h
View File

@ -3,7 +3,6 @@
#include "qemu/processor.h"
#include "qemu/atomic.h"
#include "qemu/clang-tsa.h"
typedef struct QemuCond QemuCond;
typedef struct QemuSemaphore QemuSemaphore;

1
include/qemu/typedefs.h
View File

@ -22,6 +22,7 @@
* Please keep this list in case-insensitive alphabetical order.
*/
typedef struct AccelCPUState AccelCPUState;
typedef struct AccelOpsClass AccelOpsClass;
typedef struct AccelState AccelState;
typedef struct AddressSpace AddressSpace;
typedef struct AioContext AioContext;

1
include/system/accel-ops.h
View File

@ -17,7 +17,6 @@
#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX
#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS)
typedef struct AccelOpsClass AccelOpsClass;
DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS)
/**

2
include/system/arch_init.h
View File

@ -27,6 +27,4 @@ enum {
extern const uint32_t arch_type;
void qemu_init_arch_modules(void);
#endif

4
include/system/cpus.h
View File

@ -1,8 +1,6 @@
#ifndef QEMU_CPUS_H
#define QEMU_CPUS_H
#include "system/accel-ops.h"
/* register accel-specific operations */
void cpus_register_accel(const AccelOpsClass *i);
@ -38,8 +36,6 @@ void resume_all_vcpus(void);
void pause_all_vcpus(void);
void cpu_stop_current(void);
extern int icount_align_option;
/* Unblock cpu */
void qemu_cpu_kick_self(void);

2
linux-user/signal.c
View File

@ -21,7 +21,7 @@
#include "qemu/cutils.h"
#include "gdbstub/user.h"
#include "exec/page-protection.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include <sys/ucontext.h>
#include <sys/resource.h>

9
system/arch_init.c
View File

@ -22,7 +22,6 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "system/arch_init.h"
#ifdef TARGET_SPARC
@ -40,11 +39,3 @@ int graphic_depth = 32;
#endif
const uint32_t arch_type = QEMU_ARCH;
void qemu_init_arch_modules(void)
{
#ifdef CONFIG_MODULES
module_init_info(qemu_modinfo);
module_allow_arch(TARGET_NAME);
#endif
}

1
system/cpus.c
View File

@ -31,6 +31,7 @@
#include "qapi/qapi-events-run-state.h"
#include "qapi/qmp/qerror.h"
#include "exec/gdbstub.h"
#include "system/accel-ops.h"
#include "system/hw_accel.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"

1
system/globals.c
View File

@ -58,7 +58,6 @@ unsigned int nb_prom_envs;
const char *prom_envs[MAX_PROM_ENVS];
uint8_t *boot_splash_filedata;
int only_migratable; /* turn it off unless user states otherwise */
int icount_align_option;
/* The bytes in qemu_uuid are in the order specified by RFC4122, _not_ in the
* little-endian "wire format" described in the SMBIOS 2.6 specification.

2
system/physmem.c
View File

@ -28,7 +28,7 @@
#include "qemu/lockable.h"
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "exec/exec-all.h"

7
system/vl.c
View File

@ -26,6 +26,7 @@
#include "qemu/help-texts.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/module.h"
#include "exec/cpu-common.h"
#include "exec/page-vary.h"
#include "hw/qdev-properties.h"
@ -78,6 +79,7 @@
#include "hw/block/block.h"
#include "hw/i386/x86.h"
#include "hw/i386/pc.h"
#include "hw/core/cpu.h"
#include "migration/cpr.h"
#include "migration/misc.h"
#include "migration/snapshot.h"
@ -2885,7 +2887,10 @@ void qemu_init(int argc, char **argv)
os_setup_limits();
qemu_init_arch_modules();
#ifdef CONFIG_MODULES
module_init_info(qemu_modinfo);
module_allow_arch(target_name());
#endif
qemu_init_subsystems();

3
target/alpha/cpu.c
View File

@ -85,6 +85,7 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_alpha_ev6;
info->print_insn = print_insn_alpha;
}
@ -227,7 +228,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,

15
target/alpha/fpu_helper.c
View File

@ -455,29 +455,28 @@ static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode)
{
float64 fa;
int64_t ret;
uint32_t exc;
uint32_t exc = 0;
int flags;
fa = t_to_float64(a);
ret = float64_to_int64_modulo(fa, roundmode, &FP_STATUS);
exc = get_float_exception_flags(&FP_STATUS);
if (unlikely(exc)) {
flags = get_float_exception_flags(&FP_STATUS);
if (unlikely(flags)) {
set_float_exception_flags(0, &FP_STATUS);
/* We need to massage the resulting exceptions. */
if (exc & float_flag_invalid_cvti) {
if (flags & float_flag_invalid_cvti) {
/* Overflow, either normal or infinity. */
if (float64_is_infinity(fa)) {
exc = FPCR_INV;
} else {
exc = FPCR_IOV | FPCR_INE;
}
} else if (exc & float_flag_invalid) {
} else if (flags & float_flag_invalid) {
exc = FPCR_INV;
} else if (exc & float_flag_inexact) {
} else if (flags & float_flag_inexact) {
exc = FPCR_INE;
} else {
exc = 0;
}
}
env->error_code = exc;

12
target/arm/cpu.c
View File

@ -29,7 +29,7 @@
#include "cpu.h"
#ifdef CONFIG_TCG
#include "exec/translation-block.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#endif /* CONFIG_TCG */
#include "internals.h"
#include "cpu-features.h"
@ -1171,7 +1171,7 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
{
ARMCPU *ac = ARM_CPU(cpu);
CPUARMState *env = &ac->env;
bool sctlr_b;
bool sctlr_b = arm_sctlr_b(env);
if (is_a64(env)) {
info->cap_arch = CS_ARCH_ARM64;
@ -1198,13 +1198,9 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
info->cap_mode = cap_mode;
}
sctlr_b = arm_sctlr_b(env);
info->endian = BFD_ENDIAN_LITTLE;
if (bswap_code(sctlr_b)) {
#if TARGET_BIG_ENDIAN
info->endian = BFD_ENDIAN_LITTLE;
#else
info->endian = BFD_ENDIAN_BIG;
#endif
info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
}
info->flags &= ~INSN_ARM_BE32;
#ifndef CONFIG_USER_ONLY

2
target/arm/tcg/cpu-v7m.c
View File

@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "internals.h"
#if !defined(CONFIG_USER_ONLY)

2
target/arm/tcg/cpu32.c
View File

@ -10,7 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)

2
target/arm/tcg/mte_helper.c
View File

@ -31,7 +31,7 @@
#endif
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
#include "mte_helper.h"

2
target/arm/tcg/sve_helper.c
View File

@ -28,7 +28,7 @@
#include "tcg/tcg.h"
#include "vec_internal.h"
#include "sve_ldst_internal.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#include "user/page-protection.h"
#endif

3
target/avr/cpu.c
View File

@ -102,6 +102,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType type)
static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_arch_avr;
info->print_insn = avr_print_insn;
}
@ -203,7 +204,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
.get_phys_page_debug = avr_cpu_get_phys_page_debug,
};
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,

2
target/avr/helper.c
View File

@ -22,7 +22,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"

3
target/hexagon/cpu.c
View File

@ -293,6 +293,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->print_insn = print_insn_hexagon;
info->endian = BFD_ENDIAN_LITTLE;
}
static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
@ -321,7 +322,7 @@ static void hexagon_cpu_init(Object *obj)
{
}
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,

4
target/hexagon/cpu.h
View File

@ -26,6 +26,10 @@
#include "mmvec/mmvec.h"
#include "hw/registerfields.h"
#ifndef CONFIG_USER_ONLY
#error "Hexagon does not support system emulation"
#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64

3
target/hppa/cpu.c
View File

@ -150,6 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
{
info->mach = bfd_mach_hppa20;
info->endian = BFD_ENDIAN_BIG;
info->print_insn = print_insn_hppa;
}
@ -245,7 +246,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,

9
target/i386/cpu.c
View File

@ -6563,7 +6563,7 @@ void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
*/
static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model)
{
const X86CPUVersionDefinition *vdef;
X86CPUVersion version = x86_cpu_model_resolve_version(model);
@ -6592,7 +6592,7 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
}
static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
X86CPUModel *model)
const X86CPUModel *model)
{
const X86CPUVersionDefinition *vdef;
X86CPUVersion version = x86_cpu_model_resolve_version(model);
@ -6620,7 +6620,7 @@ static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
* Load data from X86CPUDefinition into a X86CPU object.
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
*/
static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
{
const X86CPUDefinition *def = model->cpudef;
CPUX86State *env = &cpu->env;
@ -6690,7 +6690,7 @@ static const gchar *x86_gdb_arch_name(CPUState *cs)
static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
{
X86CPUModel *model = data;
const X86CPUModel *model = data;
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
@ -8691,6 +8691,7 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
info->endian = BFD_ENDIAN_LITTLE;
info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
: bfd_mach_i386_i8086);

2
target/i386/cpu.h
View File

@ -2327,7 +2327,7 @@ struct X86CPUClass {
* CPU definition, automatically loaded by instance_init if not NULL.
* Should be eventually replaced by subclass-specific property defaults.
*/
X86CPUModel *model;
const X86CPUModel *model;
bool host_cpuid_required;
int ordering;

2
target/i386/hvf/hvf-cpu.c
View File

@ -14,7 +14,7 @@
#include "system/system.h"
#include "hw/boards.h"
#include "system/hvf.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#include "hvf-i386.h"
static void hvf_cpu_max_instance_init(X86CPU *cpu)

4
target/i386/hvf/x86_decode.c
View File

@ -61,8 +61,8 @@ uint64_t sign(uint64_t val, int size)
static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
int size)
{
target_ulong val = 0;
uint64_t val = 0;
switch (size) {
case 1:
case 2:

2
target/i386/kvm/kvm-cpu.c
View File

@ -15,7 +15,7 @@
#include "hw/boards.h"
#include "kvm_i386.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
static void kvm_set_guest_phys_bits(CPUState *cs)
{

1
target/i386/nvmm/nvmm-accel-ops.c
View File

@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include "system/kvm_int.h"
#include "qemu/main-loop.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"

4
target/i386/tcg/tcg-cpu.c
View File

@ -21,7 +21,7 @@
#include "cpu.h"
#include "helper-tcg.h"
#include "qemu/accel.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#include "exec/translation-block.h"
#include "tcg-cpu.h"
@ -105,7 +105,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
}
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,

1
target/i386/whpx/whpx-accel-ops.c
View File

@ -11,6 +11,7 @@
#include "qemu/osdep.h"
#include "system/kvm_int.h"
#include "qemu/main-loop.h"
#include "system/accel-ops.h"
#include "system/cpus.h"
#include "qemu/guest-random.h"

2
target/i386/whpx/whpx-apic.c
View File

@ -231,7 +231,7 @@ static void whpx_apic_mem_write(void *opaque, hwaddr addr,
static const MemoryRegionOps whpx_apic_io_ops = {
.read = whpx_apic_mem_read,
.write = whpx_apic_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void whpx_apic_reset(APICCommonState *s)

3
target/loongarch/cpu.c
View File

@ -624,6 +624,7 @@ static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->endian = BFD_ENDIAN_LITTLE;
info->print_insn = print_insn_loongarch;
}
@ -857,7 +858,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,

3
target/m68k/cpu.c
View File

@ -157,6 +157,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
info->print_insn = print_insn_m68k;
info->endian = BFD_ENDIAN_BIG;
info->mach = 0;
}
@ -582,7 +583,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
};
#endif /* !CONFIG_USER_ONLY */
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,

4
target/microblaze/cpu.c
View File

@ -224,6 +224,8 @@ static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_arch_microblaze;
info->print_insn = print_insn_microblaze;
info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE;
}
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
@ -419,7 +421,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,

7
target/microblaze/cpu.h
View File

@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb,
/* Ensure there is no overlap between the two masks. */
QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
static inline bool mb_cpu_is_big_endian(CPUState *cs)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
return !cpu->cfg.endi;
}
static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{

5
target/microblaze/gdbstub.c
View File

@ -110,14 +110,9 @@ int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n)
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUClass *cc = CPU_GET_CLASS(cs);
CPUMBState *env = cpu_env(cs);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
switch (n) {

49
target/microblaze/translate.c
View File

@ -708,11 +708,18 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
}
#endif
static inline MemOp mo_endian(DisasContext *dc)
{
return dc->cfg->endi ? MO_LE : MO_BE;
}
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
int mem_index, bool rev)
{
MemOp size = mop & MO_SIZE;
mop |= mo_endian(dc);
/*
* When doing reverse accesses we need to do two things.
*
@ -780,13 +787,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@ -798,26 +805,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@ -829,14 +836,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@ -846,7 +853,8 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index,
mo_endian(dc) | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) {
@ -863,6 +871,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
{
MemOp size = mop & MO_SIZE;
mop |= mo_endian(dc);
/*
* When doing reverse accesses we need to do two things.
*
@ -930,13 +940,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@ -948,26 +958,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@ -979,14 +989,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
@ -1015,7 +1025,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd),
dc->mem_index, MO_TEUL);
dc->mem_index, mo_endian(dc) | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
@ -1637,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
dc->tb_flags_to_set = 0;
ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next,
mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN);
if (!decode(dc, ir)) {
trap_illegal(dc, true);
}

12
target/mips/cpu.c
View File

@ -428,13 +428,13 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
{
if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) {
#if TARGET_BIG_ENDIAN
info->print_insn = print_insn_big_mips;
#else
info->print_insn = print_insn_little_mips;
#endif
info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE;
info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips
: print_insn_little_mips;
} else {
info->print_insn = print_insn_nanomips;
info->endian = BFD_ENDIAN_LITTLE;
}
}
@ -544,7 +544,7 @@ static const Property mips_cpu_properties[] = {
};
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,

6
target/mips/tcg/msa_helper.c
View File

@ -5577,7 +5577,7 @@ static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t q_min = DF_MIN_INT(df);
int64_t q_max = DF_MAX_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = 1LL << (DF_BITS(df) - 2);
if (arg1 == q_min && arg2 == q_min) {
return q_max;
@ -5685,7 +5685,7 @@ static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = 1LL << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
@ -5700,7 +5700,7 @@ static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = 1LL << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);

7
target/openrisc/cpu.c
View File

@ -83,6 +83,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->endian = BFD_ENDIAN_BIG;
info->print_insn = print_insn_or1k;
}
@ -165,6 +166,10 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
qemu_init_vcpu(cs);
cpu_reset(cs);
#ifndef CONFIG_USER_ONLY
cpu_openrisc_clock_init(OPENRISC_CPU(dev));
#endif
occ->parent_realize(dev, errp);
}
@ -232,7 +237,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,

5
target/openrisc/gdbstub.c
View File

@ -47,14 +47,9 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUClass *cc = CPU_GET_CLASS(cs);
CPUOpenRISCState *env = cpu_env(cs);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
if (n < 32) {

4
target/ppc/cpu_init.c
View File

@ -7401,6 +7401,8 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
if ((env->hflags >> MSR_LE) & 1) {
info->endian = BFD_ENDIAN_LITTLE;
} else {
info->endian = BFD_ENDIAN_BIG;
}
info->mach = env->bfd_mach;
if (!env->bfd_mach) {
@ -7430,7 +7432,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,

2
target/ppc/kvm.c
View File

@ -49,7 +49,7 @@
#include "elf.h"
#include "system/kvm_int.h"
#include "system/kvm.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#include CONFIG_DEVICES

19
target/riscv/cpu.c
View File

@ -1152,6 +1152,15 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
CPURISCVState *env = &cpu->env;
info->target_info = &cpu->cfg;
/*
* A couple of bits in MSTATUS set the endianness:
* - MSTATUS_UBE (User-mode),
* - MSTATUS_SBE (Supervisor-mode),
* - MSTATUS_MBE (Machine-mode)
* but we don't implement that yet.
*/
info->endian = BFD_ENDIAN_LITTLE;
switch (env->xl) {
case MXL_RV32:
info->print_insn = print_insn_riscv32;
@ -3063,7 +3072,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
riscv_cpu_validate_misa_mxl(mcc);
}
@ -3165,7 +3174,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
.class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
@ -3174,7 +3183,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
.class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
@ -3183,7 +3192,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
.class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
@ -3192,7 +3201,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
.parent = TYPE_RISCV_BARE_CPU, \
.instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
.class_data = GUINT_TO_POINTER(misa_mxl_max) \
}
static const TypeInfo riscv_cpu_type_infos[] = {

2
target/riscv/cpu.h
View File

@ -539,7 +539,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t misa_mxl_max; /* max mxl for this cpu */
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)

2
target/riscv/cpu_helper.c
View File

@ -27,7 +27,7 @@
#include "exec/page-protection.h"
#include "instmap.h"
#include "tcg/tcg-op.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "trace.h"
#include "semihosting/common-semi.h"
#include "system/cpu-timers.h"

2
target/riscv/kvm/kvm-cpu.c
View File

@ -32,7 +32,7 @@
#include "system/kvm_int.h"
#include "cpu.h"
#include "trace.h"
#include "hw/core/accel-cpu.h"
#include "accel/accel-cpu-target.h"
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "exec/address-spaces.h"

4
target/riscv/tcg/tcg-cpu.c
View File

@ -30,8 +30,8 @@
#include "qemu/accel.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/core/accel-cpu.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/accel-cpu-target.h"
#include "accel/tcg/cpu-ops.h"
#include "tcg/tcg.h"
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"

9
target/rx/cpu.c
View File

@ -168,6 +168,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int request)
static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->endian = BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_rx;
info->print_insn = print_insn_rx;
}
@ -192,15 +193,13 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps rx_sysemu_ops = {
.get_phys_page_debug = rx_cpu_get_phys_page_debug,
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
@ -209,11 +208,9 @@ static const TCGCPUOps rx_tcg_ops = {
.restore_state_to_opc = rx_restore_state_to_opc,
.tlb_fill = rx_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
.cpu_exec_halt = rx_cpu_has_work,
.do_interrupt = rx_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
};
static void rx_cpu_class_init(ObjectClass *klass, void *data)
@ -235,9 +232,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->set_pc = rx_cpu_set_pc;
cc->get_pc = rx_cpu_get_pc;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &rx_sysemu_ops;
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->disas_set_info = rx_cpu_disas_set_info;

6
target/rx/cpu.h
View File

@ -26,6 +26,10 @@
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#ifdef CONFIG_USER_ONLY
#error "RX does not support user mode emulation"
#endif
/* PSW define */
REG32(PSW, 0)
FIELD(PSW, C, 0, 1)
@ -129,11 +133,9 @@ struct RXCPUClass {
#define CPU_RESOLVING_TYPE TYPE_RX_CPU
const char *rx_crname(uint8_t cr);
#ifndef CONFIG_USER_ONLY
void rx_cpu_do_interrupt(CPUState *cpu);
bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

4
target/rx/helper.c
View File

@ -40,8 +40,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
env->psw_c = FIELD_EX32(psw, PSW, C);
}
#ifndef CONFIG_USER_ONLY
#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
void rx_cpu_do_interrupt(CPUState *cs)
{
@ -146,5 +144,3 @@ hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
return addr;
}
#endif /* !CONFIG_USER_ONLY */

3
target/s390x/cpu.c
View File

@ -243,6 +243,7 @@ static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_mach_s390_64;
info->cap_arch = CS_ARCH_SYSZ;
info->endian = BFD_ENDIAN_BIG;
info->cap_insn_unit = 2;
info->cap_insn_split = 6;
}
@ -322,7 +323,7 @@ static const Property s390x_cpu_properties[] = {
#endif
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)

2
target/s390x/tcg/mem_helper.c
View File

@ -28,7 +28,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"

4
target/sh4/cpu.c
View File

@ -143,6 +143,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE;
info->mach = bfd_mach_sh4;
info->print_insn = print_insn_sh;
}
@ -256,7 +258,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
};
#endif
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,

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