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hw/isa/piix3: Drop the "3" from PIIX base class name

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TYPE_PIIX3_PCI_DEVICE was the former base class of the Xen and non-Xen variants
of the PIIX3 ISA device models. It will become the base class for the PIIX3 and
PIIX4 device models, so drop the "3" from the type names.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20231007123843.127151-15-shentey@gmail.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-10-07 14:38:22 +02:00 committed by Michael S. Tsirkin
parent 0a15cf0801
commit 9769cfc3e4
2 changed files with 30 additions and 32 deletions
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56
hw/isa/piix3.c
View File

@ -35,7 +35,7 @@
#include "migration/vmstate.h" #include "migration/vmstate.h"
#include "hw/acpi/acpi_aml_interface.h" #include "hw/acpi/acpi_aml_interface.h"
static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) static void piix3_set_irq_pic(PIIXState *piix3, int pic_irq)
{ {
qemu_set_irq(piix3->isa_irqs_in[pic_irq], qemu_set_irq(piix3->isa_irqs_in[pic_irq],
!!(piix3->pic_levels & !!(piix3->pic_levels &
@ -43,7 +43,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
(pic_irq * PIIX_NUM_PIRQS)))); (pic_irq * PIIX_NUM_PIRQS))));
} }
static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq_level_internal(PIIXState *piix3, int pirq, int level)
{ {
int pic_irq; int pic_irq;
uint64_t mask; uint64_t mask;
@ -58,7 +58,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
piix3->pic_levels |= mask * !!level; piix3->pic_levels |= mask * !!level;
} }
static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) static void piix3_set_irq_level(PIIXState *piix3, int pirq, int level)
{ {
int pic_irq; int pic_irq;
@ -74,13 +74,13 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
static void piix3_set_irq(void *opaque, int pirq, int level) static void piix3_set_irq(void *opaque, int pirq, int level)
{ {
PIIX3State *piix3 = opaque; PIIXState *piix3 = opaque;
piix3_set_irq_level(piix3, pirq, level); piix3_set_irq_level(piix3, pirq, level);
} }
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{ {
PIIX3State *piix3 = opaque; PIIXState *piix3 = opaque;
int irq = piix3->dev.config[PIIX_PIRQCA + pin]; int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route; PCIINTxRoute route;
@ -95,7 +95,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
} }
/* irq routing is changed. so rebuild bitmap */ /* irq routing is changed. so rebuild bitmap */
static void piix3_update_irq_levels(PIIX3State *piix3) static void piix3_update_irq_levels(PIIXState *piix3)
{ {
PCIBus *bus = pci_get_bus(&piix3->dev); PCIBus *bus = pci_get_bus(&piix3->dev);
int pirq; int pirq;
@ -111,7 +111,7 @@ static void piix3_write_config(PCIDevice *dev,
{ {
pci_default_write_config(dev, address, val, len); pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) { if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
int pic_irq; int pic_irq;
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
@ -124,7 +124,7 @@ static void piix3_write_config(PCIDevice *dev,
static void piix3_reset(DeviceState *dev) static void piix3_reset(DeviceState *dev)
{ {
PIIX3State *d = PIIX3_PCI_DEVICE(dev); PIIXState *d = PIIX_PCI_DEVICE(dev);
uint8_t *pci_conf = d->dev.config; uint8_t *pci_conf = d->dev.config;
pci_conf[0x04] = 0x07; /* master, memory and I/O */ pci_conf[0x04] = 0x07; /* master, memory and I/O */
@ -165,7 +165,7 @@ static void piix3_reset(DeviceState *dev)
static int piix3_post_load(void *opaque, int version_id) static int piix3_post_load(void *opaque, int version_id)
{ {
PIIX3State *piix3 = opaque; PIIXState *piix3 = opaque;
int pirq; int pirq;
/* /*
@ -188,7 +188,7 @@ static int piix3_post_load(void *opaque, int version_id)
static int piix3_pre_save(void *opaque) static int piix3_pre_save(void *opaque)
{ {
int i; int i;
PIIX3State *piix3 = opaque; PIIXState *piix3 = opaque;
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
piix3->pci_irq_levels_vmstate[i] = piix3->pci_irq_levels_vmstate[i] =
@ -200,7 +200,7 @@ static int piix3_pre_save(void *opaque)
static bool piix3_rcr_needed(void *opaque) static bool piix3_rcr_needed(void *opaque)
{ {
PIIX3State *piix3 = opaque; PIIXState *piix3 = opaque;
return (piix3->rcr != 0); return (piix3->rcr != 0);
} }
@ -211,7 +211,7 @@ static const VMStateDescription vmstate_piix3_rcr = {
.minimum_version_id = 1, .minimum_version_id = 1,
.needed = piix3_rcr_needed, .needed = piix3_rcr_needed,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT8(rcr, PIIX3State), VMSTATE_UINT8(rcr, PIIXState),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };
@ -223,8 +223,8 @@ static const VMStateDescription vmstate_piix3 = {
.post_load = piix3_post_load, .post_load = piix3_post_load,
.pre_save = piix3_pre_save, .pre_save = piix3_pre_save,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIX3State), VMSTATE_PCI_DEVICE(dev, PIIXState),
VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
PIIX_NUM_PIRQS, 3), PIIX_NUM_PIRQS, 3),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
}, },
@ -237,7 +237,7 @@ static const VMStateDescription vmstate_piix3 = {
static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
{ {
PIIX3State *d = opaque; PIIXState *d = opaque;
if (val & 4) { if (val & 4) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
@ -248,7 +248,7 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len) static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
{ {
PIIX3State *d = opaque; PIIXState *d = opaque;
return d->rcr; return d->rcr;
} }
@ -265,7 +265,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp) static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{ {
PIIX3State *d = PIIX3_PCI_DEVICE(dev); PIIXState *d = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev); PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus; ISABus *isa_bus;
uint32_t irq; uint32_t irq;
@ -345,7 +345,7 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
static void pci_piix3_init(Object *obj) static void pci_piix3_init(Object *obj)
{ {
PIIX3State *d = PIIX3_PCI_DEVICE(obj); PIIXState *d = PIIX_PCI_DEVICE(obj);
qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs", qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
ISA_NUM_IRQS); ISA_NUM_IRQS);
@ -355,10 +355,10 @@ static void pci_piix3_init(Object *obj)
} }
static Property pci_piix3_props[] = { static Property pci_piix3_props[] = {
DEFINE_PROP_UINT32("smb_io_base", PIIX3State, smb_io_base, 0), DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
DEFINE_PROP_BOOL("has-acpi", PIIX3State, has_acpi, true), DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true), DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
DEFINE_PROP_BOOL("smm-enabled", PIIX3State, smm_enabled, false), DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -386,10 +386,10 @@ static void pci_piix3_class_init(ObjectClass *klass, void *data)
adevc->build_dev_aml = build_pci_isa_aml; adevc->build_dev_aml = build_pci_isa_aml;
} }
static const TypeInfo piix3_pci_type_info = { static const TypeInfo piix_pci_type_info = {
.name = TYPE_PIIX3_PCI_DEVICE, .name = TYPE_PIIX_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE, .parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIX3State), .instance_size = sizeof(PIIXState),
.instance_init = pci_piix3_init, .instance_init = pci_piix3_init,
.abstract = true, .abstract = true,
.class_init = pci_piix3_class_init, .class_init = pci_piix3_class_init,
@ -403,7 +403,7 @@ static const TypeInfo piix3_pci_type_info = {
static void piix3_realize(PCIDevice *dev, Error **errp) static void piix3_realize(PCIDevice *dev, Error **errp)
{ {
ERRP_GUARD(); ERRP_GUARD();
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev); PIIXState *piix3 = PIIX_PCI_DEVICE(dev);
PCIBus *pci_bus = pci_get_bus(dev); PCIBus *pci_bus = pci_get_bus(dev);
pci_piix3_realize(dev, errp); pci_piix3_realize(dev, errp);
@ -424,13 +424,13 @@ static void piix3_class_init(ObjectClass *klass, void *data)
static const TypeInfo piix3_info = { static const TypeInfo piix3_info = {
.name = TYPE_PIIX3_DEVICE, .name = TYPE_PIIX3_DEVICE,
.parent = TYPE_PIIX3_PCI_DEVICE, .parent = TYPE_PIIX_PCI_DEVICE,
.class_init = piix3_class_init, .class_init = piix3_class_init,
}; };
static void piix3_register_types(void) static void piix3_register_types(void)
{ {
type_register_static(&piix3_pci_type_info); type_register_static(&piix_pci_type_info);
type_register_static(&piix3_info); type_register_static(&piix3_info);
} }

6
include/hw/southbridge/piix.h
View File

@ -71,11 +71,9 @@ struct PIIXState {
bool has_usb; bool has_usb;
bool smm_enabled; bool smm_enabled;
}; };
typedef struct PIIXState PIIX3State;
#define TYPE_PIIX3_PCI_DEVICE "pci-piix3" #define TYPE_PIIX_PCI_DEVICE "pci-piix"
DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
TYPE_PIIX3_PCI_DEVICE)
#define TYPE_PIIX3_DEVICE "PIIX3" #define TYPE_PIIX3_DEVICE "PIIX3"
#define TYPE_PIIX4_PCI_DEVICE "piix4-isa" #define TYPE_PIIX4_PCI_DEVICE "piix4-isa"