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target/arm: Implement RMR_ELx

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Provide a stub implementation, as a write is a "request".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230831232441.66020-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2023-08-31 16:24:37 -07:00 committed by Peter Maydell
parent 682814e2a3
commit 97198a7dd1
1 changed files with 41 additions and 23 deletions
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50
target/arm/helper.c
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@ -8682,16 +8682,25 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}; };
modify_arm_cp_regs(v8_idregs, v8_user_idregs); modify_arm_cp_regs(v8_idregs, v8_user_idregs);
#endif #endif
/* RVBAR_EL1 is only implemented if EL1 is the highest EL */ /*
* RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
* TODO: For RMR, a write with bit 1 set should do something with
* cpu_reset(). In the meantime, "the bit is strictly a request",
* so we are in spec just ignoring writes.
*/
if (!arm_feature(env, ARM_FEATURE_EL3) && if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) { !arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar = { ARMCPRegInfo el1_reset_regs[] = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH, { .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL1_R, .access = PL1_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar) },
{ .name = "RMR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST,
.resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) }
}; };
define_one_arm_cp_reg(cpu, &rvbar); define_arm_cp_regs(cpu, el1_reset_regs);
} }
define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo); define_arm_cp_regs(cpu, v8_cp_reginfo);
@ -8775,22 +8784,25 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_sel2, cpu)) { if (cpu_isar_feature(aa64_sel2, cpu)) {
define_arm_cp_regs(cpu, el2_sec_cp_reginfo); define_arm_cp_regs(cpu, el2_sec_cp_reginfo);
} }
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */ /*
* RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
* See commentary near RMR_EL1.
*/
if (!arm_feature(env, ARM_FEATURE_EL3)) { if (!arm_feature(env, ARM_FEATURE_EL3)) {
ARMCPRegInfo rvbar[] = { static const ARMCPRegInfo el2_reset_regs[] = {
{ { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL2_R, .access = PL2_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar) },
},
{ .name = "RVBAR", .type = ARM_CP_ALIAS, { .name = "RVBAR", .type = ARM_CP_ALIAS,
.cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL2_R, .access = PL2_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar) },
}, { .name = "RMR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 2,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 1 },
}; };
define_arm_cp_regs(cpu, rvbar); define_arm_cp_regs(cpu, el2_reset_regs);
} }
} }
@ -8801,8 +8813,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL3_R, .access = PL3_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar), },
}, { .name = "RMR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2,
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 1 },
{ .name = "RMR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
.access = PL3_RW, .type = ARM_CP_CONST,
.resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW, .access = PL3_RW,