vfio/pci: Rework RTL8168 quirk
Another rework of this quirk, this time to update to the new quirk structure. We can handle the address and data registers with separate MemoryRegions and a quirk specific data structure, making the code much more understandable. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
This commit is contained in:
Alex Williamson
parent
6029a424be
commit
954258a5f1
@ -784,81 +784,63 @@ static void vfio_probe_nvidia_bar0_1800_quirk(VFIOPCIDevice *vdev, int nr)
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* vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write
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* vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete
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*/
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static uint64_t vfio_rtl8168_window_quirk_read(void *opaque,
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hwaddr addr, unsigned size)
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typedef struct VFIOrtl8168Quirk {
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VFIOPCIDevice *vdev;
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uint32_t addr;
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uint32_t data;
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bool enabled;
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} VFIOrtl8168Quirk;
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static uint64_t vfio_rtl8168_quirk_address_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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VFIOLegacyQuirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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uint64_t val = 0;
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VFIOrtl8168Quirk *rtl = opaque;
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VFIOPCIDevice *vdev = rtl->vdev;
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uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x74, size);
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if (!quirk->data.flags) { /* Non-MSI-X table access */
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return vfio_region_read(&vdev->bars[quirk->data.bar].region,
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addr + 0x70, size);
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if (rtl->enabled) {
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data = rtl->addr ^ 0x80000000U; /* latch/complete */
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trace_vfio_quirk_rtl8168_fake_latch(vdev->vbasedev.name, data);
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}
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switch (addr) {
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case 4: /* address */
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val = quirk->data.address_match ^ 0x80000000U; /* latch/complete */
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break;
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case 0: /* data */
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if ((vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
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memory_region_dispatch_read(&vdev->pdev.msix_table_mmio,
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(hwaddr)(quirk->data.address_match & 0xfff),
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&val, size, MEMTXATTRS_UNSPECIFIED);
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}
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break;
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}
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trace_vfio_rtl8168_quirk_read(vdev->vbasedev.name,
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addr ? "address" : "data", val);
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return val;
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return data;
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}
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static void vfio_rtl8168_window_quirk_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOLegacyQuirk *quirk = opaque;
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VFIOPCIDevice *vdev = quirk->vdev;
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VFIOrtl8168Quirk *rtl = opaque;
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VFIOPCIDevice *vdev = rtl->vdev;
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switch (addr) {
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case 4: /* address */
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if ((data & 0x7fff0000) == 0x10000) { /* MSI-X table */
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quirk->data.flags = 1; /* Activate reads */
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quirk->data.address_match = data;
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rtl->enabled = false;
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trace_vfio_rtl8168_quirk_write(vdev->vbasedev.name, data);
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if ((data & 0x7fff0000) == 0x10000) { /* MSI-X table */
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rtl->enabled = true;
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rtl->addr = (uint32_t)data;
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if (data & 0x80000000U) { /* Do write */
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if (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX) {
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hwaddr offset = data & 0xfff;
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uint64_t val = quirk->data.address_mask;
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if (data & 0x80000000U) { /* Do write */
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if (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX) {
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hwaddr offset = data & 0xfff;
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uint64_t val = rtl->data;
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trace_vfio_rtl8168_quirk_msix(vdev->vbasedev.name,
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(uint16_t)offset, val);
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trace_vfio_quirk_rtl8168_msix_write(vdev->vbasedev.name,
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(uint16_t)offset, val);
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/* Write to the proper guest MSI-X table instead */
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memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
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offset, val, size,
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MEMTXATTRS_UNSPECIFIED);
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}
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return; /* Do not write guest MSI-X data to hardware */
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/* Write to the proper guest MSI-X table instead */
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memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
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offset, val, size,
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MEMTXATTRS_UNSPECIFIED);
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}
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} else {
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quirk->data.flags = 0; /* De-activate reads, non-MSI-X */
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return; /* Do not write guest MSI-X data to hardware */
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}
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break;
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case 0: /* data */
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quirk->data.address_mask = data;
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break;
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}
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vfio_region_write(&vdev->bars[quirk->data.bar].region,
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addr + 0x70, data, size);
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vfio_region_write(&vdev->bars[2].region, addr + 0x74, data, size);
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}
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static const MemoryRegionOps vfio_rtl8168_window_quirk = {
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.read = vfio_rtl8168_window_quirk_read,
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.write = vfio_rtl8168_window_quirk_write,
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static const MemoryRegionOps vfio_rtl_address_quirk = {
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.read = vfio_rtl8168_quirk_address_read,
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.write = vfio_rtl8168_quirk_address_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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@ -867,32 +849,75 @@ static const MemoryRegionOps vfio_rtl8168_window_quirk = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void vfio_probe_rtl8168_bar2_window_quirk(VFIOPCIDevice *vdev, int nr)
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static uint64_t vfio_rtl8168_quirk_data_read(void *opaque,
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hwaddr addr, unsigned size)
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{
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PCIDevice *pdev = &vdev->pdev;
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VFIOQuirk *quirk;
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VFIOLegacyQuirk *legacy;
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VFIOrtl8168Quirk *rtl = opaque;
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VFIOPCIDevice *vdev = rtl->vdev;
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uint64_t data = vfio_region_read(&vdev->bars[2].region, addr + 0x74, size);
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if (pci_get_word(pdev->config + PCI_VENDOR_ID) != PCI_VENDOR_ID_REALTEK ||
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pci_get_word(pdev->config + PCI_DEVICE_ID) != 0x8168 || nr != 2) {
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if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
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hwaddr offset = rtl->addr & 0xfff;
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memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,
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&data, size, MEMTXATTRS_UNSPECIFIED);
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trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);
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}
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return data;
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}
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static void vfio_rtl8168_quirk_data_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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VFIOrtl8168Quirk *rtl = opaque;
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VFIOPCIDevice *vdev = rtl->vdev;
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rtl->data = (uint32_t)data;
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vfio_region_write(&vdev->bars[2].region, addr + 0x70, data, size);
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}
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static const MemoryRegionOps vfio_rtl_data_quirk = {
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.read = vfio_rtl8168_quirk_data_read,
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.write = vfio_rtl8168_quirk_data_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void vfio_probe_rtl8168_bar2_quirk(VFIOPCIDevice *vdev, int nr)
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{
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VFIOQuirk *quirk;
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VFIOrtl8168Quirk *rtl;
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if (!vfio_pci_is(vdev, PCI_VENDOR_ID_REALTEK, 0x8168) || nr != 2) {
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return;
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}
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quirk = g_malloc0(sizeof(*quirk));
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quirk->data = legacy = g_malloc0(sizeof(*legacy));
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quirk->mem = legacy->mem = g_malloc0_n(sizeof(MemoryRegion), 1);
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quirk->nr_mem = 1;
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legacy->vdev = vdev;
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legacy->data.bar = nr;
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quirk->mem = g_malloc0_n(sizeof(MemoryRegion), 2);
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quirk->nr_mem = 2;
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quirk->data = rtl = g_malloc0(sizeof(*rtl));
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rtl->vdev = vdev;
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memory_region_init_io(quirk->mem, OBJECT(vdev), &vfio_rtl8168_window_quirk,
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legacy, "vfio-rtl8168-window-quirk", 8);
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memory_region_init_io(&quirk->mem[0], OBJECT(vdev),
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&vfio_rtl_address_quirk, rtl,
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"vfio-rtl8168-window-address-quirk", 4);
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memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem,
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0x70, quirk->mem, 1);
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0x74, &quirk->mem[0], 1);
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memory_region_init_io(&quirk->mem[1], OBJECT(vdev),
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&vfio_rtl_data_quirk, rtl,
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"vfio-rtl8168-window-data-quirk", 4);
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memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem,
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0x70, &quirk->mem[1], 1);
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QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
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trace_vfio_rtl8168_quirk_enable(vdev->vbasedev.name);
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trace_vfio_quirk_rtl8168_probe(vdev->vbasedev.name);
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}
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/*
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@ -944,7 +969,7 @@ void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr)
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vfio_probe_nvidia_bar5_window_quirk(vdev, nr);
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vfio_probe_nvidia_bar0_88000_quirk(vdev, nr);
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vfio_probe_nvidia_bar0_1800_quirk(vdev, nr);
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vfio_probe_rtl8168_bar2_window_quirk(vdev, nr);
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vfio_probe_rtl8168_bar2_quirk(vdev, nr);
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}
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void vfio_bar_quirk_teardown(VFIOPCIDevice *vdev, int nr)
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@ -1552,10 +1552,6 @@ vfio_generic_quirk_read(const char * region_name, const char *name, int index, u
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vfio_generic_quirk_write(const char * region_name, const char *name, int index, uint64_t addr, uint64_t data, int size) "%s write(%s:BAR%d+0x%"PRIx64", 0x%"PRIx64", %d"
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vfio_probe_ati_bar4_window_quirk(const char *name) "Enabled ATI/AMD BAR4 window quirk for device %s"
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#issue with )
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vfio_rtl8168_quirk_read(const char *name, const char *type, uint64_t val) "%s [%s]: 0x%"PRIx64
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vfio_rtl8168_quirk_write(const char *name, uint64_t val) "%s [address]: 0x%"PRIx64
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vfio_rtl8168_quirk_msix(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64
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vfio_rtl8168_quirk_enable(const char *name) "%s"
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vfio_probe_ati_bar2_4000_quirk(const char *name) "Enabled ATI/AMD BAR2 0x4000 quirk for device %s"
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vfio_probe_nvidia_bar5_window_quirk(const char *name) "Enabled NVIDIA BAR5 window quirk for device %s"
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vfio_probe_nvidia_bar0_88000_quirk(const char *name) "Enabled NVIDIA BAR0 0x88000 quirk for device %s"
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@ -1588,6 +1584,10 @@ vfio_quirk_nvidia_3d0_state(const char *name, const char *state) "%s %s"
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vfio_quirk_nvidia_3d0_read(const char *name, uint8_t offset, unsigned size, uint64_t val) " (%s, @0x%x, len=0x%x) %"PRIx64
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vfio_quirk_nvidia_3d0_write(const char *name, uint8_t offset, uint64_t data, unsigned size) "(%s, @0x%x, 0x%"PRIx64", len=0x%x)"
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vfio_quirk_nvidia_3d0_probe(const char *name) "%s"
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vfio_quirk_rtl8168_fake_latch(const char *name, uint64_t val) "%s 0x%"PRIx64
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vfio_quirk_rtl8168_msix_write(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table write[0x%x]: 0x%"PRIx64
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vfio_quirk_rtl8168_msix_read(const char *name, uint16_t offset, uint64_t val) "%s MSI-X table read[0x%x]: 0x%"PRIx64
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vfio_quirk_rtl8168_probe(const char *name) "%s"
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# hw/vfio/vfio-common.c
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vfio_region_write(const char *name, int index, uint64_t addr, uint64_t data, unsigned size) " (%s:region%d+0x%"PRIx64", 0x%"PRIx64 ", %d)"
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