SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target/riscv: Simplify getting RISCVCPU pointer from env

Browse Source 
Use env_archcpu() to get RISCVCPU pointer from env directly.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-10-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Bin Meng 2023-02-28 18:40:25 +08:00 committed by Palmer Dabbelt
parent 77ad639cb1
commit 94e297071b
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
1 changed files with 12 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
target/riscv/csr.c
View File

@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
uint64_t bit) uint64_t bit)
{ {
bool virt = riscv_cpu_virt_enabled(env); bool virt = riscv_cpu_virt_enabled(env);
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (env->misa_ext & RVV || if (env->misa_ext & RVV ||
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno) static RISCVException ctr(CPURISCVState *env, int csrno)
{ {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index; int ctr_index;
target_ulong ctr_mask; target_ulong ctr_mask;
int base_csrno = CSR_CYCLE; int base_csrno = CSR_CYCLE;
@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno) static RISCVException mctr(CPURISCVState *env, int csrno)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index; int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3; int base_csrno = CSR_MHPMCOUNTER3;
@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno) static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_sscofpmf) { if (!cpu->cfg.ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno) static RISCVException mstateen(CPURISCVState *env, int csrno)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) { if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) { if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
{ {
bool virt = riscv_cpu_virt_enabled(env); bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0; int index = csrno - CSR_SSTATEEN0;
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
if (!cpu->cfg.ext_smstateen) { if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
static RISCVException sstc(CPURISCVState *env, int csrno) static RISCVException sstc(CPURISCVState *env, int csrno)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
bool hmode_check = false; bool hmode_check = false;
if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.mvendorid; *val = cpu->cfg.mvendorid;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
static RISCVException read_marchid(CPURISCVState *env, int csrno, static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.marchid; *val = cpu->cfg.marchid;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
static RISCVException read_mimpid(CPURISCVState *env, int csrno, static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val) target_ulong *val)
{ {
CPUState *cs = env_cpu(env); RISCVCPU *cpu = env_archcpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
*val = cpu->cfg.mimpid; *val = cpu->cfg.mimpid;
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;