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target/riscv/cpu.c: create flag for ziccrse

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At this moment ziccrse is a TCG always enabled named feature for
priv_ver > 1.11 that has no exclusive flag. In the next patch we'll make
the KVM driver turn ziccrse off if the extension isn't available in the
host, and we'll need an ext_ziccrse flag in the CPU state for that.

Create an exclusive flag for it like we do with other named features.
As with any named features we already have, it won't be exposed to
users.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20250221153758.652078-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2025-02-21 12:37:57 -03:00 committed by Alistair Francis
parent 421ee1ec6f
commit 93e59c8b76
3 changed files with 7 additions and 1 deletions
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3
target/riscv/cpu.c
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@ -105,7 +105,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, ext_ziccrse),
ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp), ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp),
ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss), ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss),
ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
@ -1742,6 +1742,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
MULTI_EXT_CFG_BOOL("sha", ext_sha, true), MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
{ }, { },
}; };

3
target/riscv/cpu_cfg.h
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@ -166,6 +166,9 @@ struct RISCVCPUConfig {
bool has_priv_1_12; bool has_priv_1_12;
bool has_priv_1_11; bool has_priv_1_11;
/* Always enabled for TCG if has_priv_1_11 */
bool ext_ziccrse;
/* Vendor-specific custom extensions */ /* Vendor-specific custom extensions */
bool ext_xtheadba; bool ext_xtheadba;
bool ext_xtheadbb; bool ext_xtheadbb;

2
target/riscv/tcg/tcg-cpu.c
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@ -360,6 +360,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) &&
cpu->cfg.ext_ssstateen; cpu->cfg.ext_ssstateen;
cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;
} }
static void riscv_cpu_validate_g(RISCVCPU *cpu) static void riscv_cpu_validate_g(RISCVCPU *cpu)