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hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs

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Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:

  IT_Lines_Number

          b00010 = the distributor provides 96 interrupts,
                   64 external interrupt lines.

Add a GIC_EXT_IRQS definition (with a comment) to make the number of
GIC external IRQs explicit.

Except explicitly setting a property value to its same implicit
value, there is no logical change intended.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-02-12 16:43:30 +01:00 committed by Peter Maydell
parent 2d269a8bbb
commit 92fea7f2e7
1 changed files with 6 additions and 3 deletions
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9
hw/arm/xilinx_zynq.c
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@ -57,6 +57,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
#define MPCORE_PERIPHBASE 0xF8F00000 #define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090 #define ZYNQ_BOARD_MIDR 0x413FC090
#define GIC_EXT_IRQS 64 /* Zynq 7000 SoC */
static const int dma_irqs[8] = { static const int dma_irqs[8] = {
46, 47, 48, 49, 72, 73, 74, 75 46, 47, 48, 49, 72, 73, 74, 75
}; };
@ -205,7 +207,7 @@ static void zynq_init(MachineState *machine)
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev, *slcr; DeviceState *dev, *slcr;
SysBusDevice *busdev; SysBusDevice *busdev;
qemu_irq pic[64]; qemu_irq pic[GIC_EXT_IRQS];
int n; int n;
unsigned int smp_cpus = machine->smp.cpus; unsigned int smp_cpus = machine->smp.cpus;
@ -261,6 +263,7 @@ static void zynq_init(MachineState *machine)
dev = qdev_new(TYPE_A9MPCORE_PRIV); dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);
busdev = SYS_BUS_DEVICE(dev); busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal); sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
@ -275,7 +278,7 @@ static void zynq_init(MachineState *machine)
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
} }
for (n = 0; n < 64; n++) { for (n = 0; n < GIC_EXT_IRQS; n++) {
pic[n] = qdev_get_gpio_in(dev, n); pic[n] = qdev_get_gpio_in(dev, n);
} }
@ -458,7 +461,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
}; };
MachineClass *mc = MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc);
ObjectProperty *prop; ObjectProperty *prop;
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9";
mc->init = zynq_init; mc->init = zynq_init;
mc->max_cpus = ZYNQ_MAX_CPUS; mc->max_cpus = ZYNQ_MAX_CPUS;
mc->ignore_memory_transaction_failures = true; mc->ignore_memory_transaction_failures = true;