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target/arm: Convert BFDOT to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-06-25 11:35:30 -07:00 committed by Peter Maydell
parent 849b7c1661
commit 9130827c4c
2 changed files with 7 additions and 15 deletions
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2
target/arm/tcg/a64.decode
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@ -950,6 +950,7 @@ SQRDMLSH_v 0.10 1110 ..0 ..... 10001 1 ..... ..... @qrrr_e
SDOT_v 0.00 1110 100 ..... 10010 1 ..... ..... @qrrr_s SDOT_v 0.00 1110 100 ..... 10010 1 ..... ..... @qrrr_s
UDOT_v 0.10 1110 100 ..... 10010 1 ..... ..... @qrrr_s UDOT_v 0.10 1110 100 ..... 10010 1 ..... ..... @qrrr_s
USDOT_v 0.00 1110 100 ..... 10011 1 ..... ..... @qrrr_s USDOT_v 0.00 1110 100 ..... 10011 1 ..... ..... @qrrr_s
BFDOT_v 0.10 1110 010 ..... 11111 1 ..... ..... @qrrr_s
### Advanced SIMD scalar x indexed element ### Advanced SIMD scalar x indexed element
@ -1029,6 +1030,7 @@ SDOT_vi 0.00 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s
UDOT_vi 0.10 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s UDOT_vi 0.10 1111 10 .. .... 1110 . 0 ..... ..... @qrrx_s
SUDOT_vi 0.00 1111 00 .. .... 1111 . 0 ..... ..... @qrrx_s SUDOT_vi 0.00 1111 00 .. .... 1111 . 0 ..... ..... @qrrx_s
USDOT_vi 0.00 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s USDOT_vi 0.00 1111 10 .. .... 1111 . 0 ..... ..... @qrrx_s
BFDOT_vi 0.00 1111 01 .. .... 1111 . 0 ..... ..... @qrrx_s
# Floating-point conditional select # Floating-point conditional select

20
target/arm/tcg/translate-a64.c
View File

@ -5604,6 +5604,7 @@ static bool do_dot_vector(DisasContext *s, arg_qrrr_e *a,
TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_sdot_b) TRANS_FEAT(SDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_sdot_b)
TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b) TRANS_FEAT(UDOT_v, aa64_dp, do_dot_vector, a, gen_helper_gvec_udot_b)
TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b) TRANS_FEAT(USDOT_v, aa64_i8mm, do_dot_vector, a, gen_helper_gvec_usdot_b)
TRANS_FEAT(BFDOT_v, aa64_bf16, do_dot_vector, a, gen_helper_gvec_bfdot)
/* /*
* Advanced SIMD scalar/vector x indexed element * Advanced SIMD scalar/vector x indexed element
@ -5942,6 +5943,8 @@ TRANS_FEAT(SUDOT_vi, aa64_i8mm, do_dot_vector_idx, a,
gen_helper_gvec_sudot_idx_b) gen_helper_gvec_sudot_idx_b)
TRANS_FEAT(USDOT_vi, aa64_i8mm, do_dot_vector_idx, a, TRANS_FEAT(USDOT_vi, aa64_i8mm, do_dot_vector_idx, a,
gen_helper_gvec_usdot_idx_b) gen_helper_gvec_usdot_idx_b)
TRANS_FEAT(BFDOT_vi, aa64_bf16, do_dot_vector_idx, a,
gen_helper_gvec_bfdot_idx)
/* /*
* Advanced SIMD scalar pairwise * Advanced SIMD scalar pairwise
@ -10951,11 +10954,11 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
break; break;
case 0x1f: case 0x1f:
switch (size) { switch (size) {
case 1: /* BFDOT */
case 3: /* BFMLAL{B,T} */ case 3: /* BFMLAL{B,T} */
feature = dc_isar_feature(aa64_bf16, s); feature = dc_isar_feature(aa64_bf16, s);
break; break;
default: default:
case 1: /* BFDOT */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
@ -11036,9 +11039,6 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
return; return;
case 0xf: case 0xf:
switch (size) { switch (size) {
case 1: /* BFDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, 0, gen_helper_gvec_bfdot);
break;
case 3: /* BFMLAL{B,T} */ case 3: /* BFMLAL{B,T} */
gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, false, is_q, gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, false, is_q,
gen_helper_gvec_bfmlal); gen_helper_gvec_bfmlal);
@ -12053,13 +12053,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
break; break;
case 0x0f: case 0x0f:
switch (size) { switch (size) {
case 1: /* BFDOT */
if (is_scalar || !dc_isar_feature(aa64_bf16, s)) {
unallocated_encoding(s);
return;
}
size = MO_32;
break;
case 3: /* BFMLAL{B,T} */ case 3: /* BFMLAL{B,T} */
if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { if (is_scalar || !dc_isar_feature(aa64_bf16, s)) {
unallocated_encoding(s); unallocated_encoding(s);
@ -12070,6 +12063,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
break; break;
default: default:
case 0: /* SUDOT */ case 0: /* SUDOT */
case 1: /* BFDOT */
case 2: /* USDOT */ case 2: /* USDOT */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
@ -12179,10 +12173,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
switch (16 * u + opcode) { switch (16 * u + opcode) {
case 0x0f: case 0x0f:
switch (extract32(insn, 22, 2)) { switch (extract32(insn, 22, 2)) {
case 1: /* BFDOT */
gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index,
gen_helper_gvec_bfdot_idx);
return;
case 3: /* BFMLAL{B,T} */ case 3: /* BFMLAL{B,T} */
gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, 0, (index << 1) | is_q, gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, 0, (index << 1) | is_q,
gen_helper_gvec_bfmlal_idx); gen_helper_gvec_bfmlal_idx);