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target/riscv: fix inverted checks for ext_zb[abcs]

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While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS]
inadvertently became inverted and slipped through the initial testing (which
used RV64GC_XVentanaCondOps as a target).
This fixes the regression.

Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs.

Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through DisasContext")
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Philipp Tomsich 2022-02-03 16:39:45 +01:00 committed by Alistair Francis
parent 64ada298b9
commit 90f9e35b78
1 changed files with 4 additions and 4 deletions
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8
target/riscv/insn_trans/trans_rvb.c.inc
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@ -19,25 +19,25 @@
*/ */
#define REQUIRE_ZBA(ctx) do { \ #define REQUIRE_ZBA(ctx) do { \
if (ctx->cfg_ptr->ext_zba) { \ if (!ctx->cfg_ptr->ext_zba) { \
return false; \ return false; \
} \ } \
} while (0) } while (0)
#define REQUIRE_ZBB(ctx) do { \ #define REQUIRE_ZBB(ctx) do { \
if (ctx->cfg_ptr->ext_zbb) { \ if (!ctx->cfg_ptr->ext_zbb) { \
return false; \ return false; \
} \ } \
} while (0) } while (0)
#define REQUIRE_ZBC(ctx) do { \ #define REQUIRE_ZBC(ctx) do { \
if (ctx->cfg_ptr->ext_zbc) { \ if (!ctx->cfg_ptr->ext_zbc) { \
return false; \ return false; \
} \ } \
} while (0) } while (0)
#define REQUIRE_ZBS(ctx) do { \ #define REQUIRE_ZBS(ctx) do { \
if (ctx->cfg_ptr->ext_zbs) { \ if (!ctx->cfg_ptr->ext_zbs) { \
return false; \ return false; \
} \ } \
} while (0) } while (0)