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target/i386: fix TCG UCODE_REV access

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This was a very interesting semantic conflict that caused git to move
the MSR_IA32_UCODE_REV read to helper_wrmsr.  Not a big deal, but
still should be fixed...

Fixes: 4e45aff398 ("target/i386: add a ucode-rev property", 2020-01-24)
Message-id: <20200206171022.9289-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2020-02-06 18:10:22 +01:00
parent 4cc600d229
commit 9028c75c9d
1 changed files with 4 additions and 4 deletions
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8
target/i386/misc_helper.c
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@ -229,7 +229,6 @@ void helper_rdmsr(CPUX86State *env)
#else #else
void helper_wrmsr(CPUX86State *env) void helper_wrmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env);
uint64_t val; uint64_t val;
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
@ -372,9 +371,6 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val; env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env); cpu_sync_bndcs_hflags(env);
break; break;
case MSR_IA32_UCODE_REV:
val = x86_cpu->ucode_rev;
break;
default: default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
@ -393,6 +389,7 @@ void helper_wrmsr(CPUX86State *env)
void helper_rdmsr(CPUX86State *env) void helper_rdmsr(CPUX86State *env)
{ {
X86CPU *x86_cpu = env_archcpu(env);
uint64_t val; uint64_t val;
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC()); cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());
@ -526,6 +523,9 @@ void helper_rdmsr(CPUX86State *env)
case MSR_IA32_BNDCFGS: case MSR_IA32_BNDCFGS:
val = env->msr_bndcfgs; val = env->msr_bndcfgs;
break; break;
case MSR_IA32_UCODE_REV:
val = x86_cpu->ucode_rev;
break;
default: default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +