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hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test

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Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.

Introduce a new "use_crypt_workaround" class attribute and set it to true in
the AST2700 HACE model to enable this workaround by default for AST2700.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-02-25 15:56:21 +08:00 committed by Cédric Le Goater
parent 7b5d6b47a6
commit 8e002a6931
2 changed files with 24 additions and 0 deletions
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23
hw/misc/aspeed_hace.c
View File

@ -59,6 +59,7 @@
/* Other cmd bits */
#define HASH_IRQ_EN BIT(9)
#define HASH_SG_EN BIT(18)
#define CRYPT_IRQ_EN BIT(12)
/* Scatter-gather data list */
#define SG_LIST_LEN_SIZE 4
#define SG_LIST_LEN_MASK 0x0FFFFFFF
@ -343,6 +344,15 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
qemu_irq_lower(s->irq);
}
}
if (ahc->raise_crypt_interrupt_workaround) {
if (data & CRYPT_IRQ) {
data &= ~CRYPT_IRQ;
if (s->regs[addr] & CRYPT_IRQ) {
qemu_irq_lower(s->irq);
}
}
}
break;
case R_HASH_SRC:
data &= ahc->src_mask;
@ -388,6 +398,12 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
case R_CRYPT_CMD:
qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n",
__func__);
if (ahc->raise_crypt_interrupt_workaround) {
s->regs[R_STATUS] |= CRYPT_IRQ;
if (data & CRYPT_IRQ_EN) {
qemu_irq_raise(s->irq);
}
}
break;
default:
break;
@ -563,6 +579,13 @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, void *data)
ahc->dest_mask = 0x7FFFFFF8;
ahc->key_mask = 0x7FFFFFF8;
ahc->hash_mask = 0x00147FFF;
/*
* Currently, it does not support the CRYPT command. Instead, it only
* sends an interrupt to notify the firmware that the crypt command
* has completed. It is a temporary workaround.
*/
ahc->raise_crypt_interrupt_workaround = true;
}
static const TypeInfo aspeed_ast2700_hace_info = {

1
include/hw/misc/aspeed_hace.h
View File

@ -50,6 +50,7 @@ struct AspeedHACEClass {
uint32_t dest_mask;
uint32_t key_mask;
uint32_t hash_mask;
bool raise_crypt_interrupt_workaround;
};
#endif /* ASPEED_HACE_H */