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target/riscv: Enforce WARL behavior for scounteren/hcounteren

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scounteren/hcountern are also WARL registers similar to mcountern.
Only set the bits for the available counters during the write to
preserve the WARL behavior.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240711-smcntrpmf_v7-v8-9-b7c38ae7b263@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2024-07-11 15:31:12 -07:00 committed by Alistair Francis
parent 46023470e0
commit 8cff74c26d
1 changed files with 10 additions and 2 deletions
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12
target/riscv/csr.c
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@ -3063,7 +3063,11 @@ static RISCVException read_scounteren(CPURISCVState *env, int csrno,
static RISCVException write_scounteren(CPURISCVState *env, int csrno, static RISCVException write_scounteren(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
env->scounteren = val; RISCVCPU *cpu = env_archcpu(env);
/* WARL register - disable unavailable counters */
env->scounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
COUNTEREN_IR);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
@ -3722,7 +3726,11 @@ static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
static RISCVException write_hcounteren(CPURISCVState *env, int csrno, static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
target_ulong val) target_ulong val)
{ {
env->hcounteren = val; RISCVCPU *cpu = env_archcpu(env);
/* WARL register - disable unavailable counters */
env->hcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
COUNTEREN_IR);
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }