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target/riscv: Coding style fixes in csr.c

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Fix various places that violate QEMU coding style:

- correct multi-line comment format
- indent to opening parenthesis

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-7-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Bin Meng 2023-02-28 18:40:22 +08:00 committed by Palmer Dabbelt
parent e17e2c7cb9
commit 8c7feddddd
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1 changed files with 32 additions and 30 deletions
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target/riscv/csr.c
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@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
/* 'E' excludes all other extensions */ /* 'E' excludes all other extensions */
if (val & RVE) { if (val & RVE) {
/* when we support 'E' we can do "val = RVE;" however /*
* when we support 'E' we can do "val = RVE;" however
* for now we just drop writes if 'E' is present. * for now we just drop writes if 'E' is present.
*/ */
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
@ -1361,7 +1362,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
val &= ~RVD; val &= ~RVD;
} }
/* Suppress 'C' if next instruction is not aligned /*
* Suppress 'C' if next instruction is not aligned
* TODO: this should check next_pc * TODO: this should check next_pc
*/ */
if ((val & RVC) && (GETPC() & ~3) != 0) { if ((val & RVC) && (GETPC() & ~3) != 0) {