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ppc/xive: Export priority_to_ipb() helper

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Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210901094153.227671-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2021-09-01 11:41:51 +02:00 committed by David Gibson
parent 0e5e9ff455
commit 89d2468d96
2 changed files with 17 additions and 15 deletions
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21
hw/intc/xive.c
View File

@ -27,17 +27,6 @@
* XIVE Thread Interrupt Management context * XIVE Thread Interrupt Management context
*/ */
/*
* Convert a priority number to an Interrupt Pending Buffer (IPB)
* register, which indicates a pending interrupt at the priority
* corresponding to the bit number
*/
static uint8_t priority_to_ipb(uint8_t priority)
{
return priority > XIVE_PRIORITY_MAX ?
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
/* /*
* Convert an Interrupt Pending Buffer (IPB) register to a Pending * Convert an Interrupt Pending Buffer (IPB) register to a Pending
* Interrupt Priority Register (PIPR), which contains the priority of * Interrupt Priority Register (PIPR), which contains the priority of
@ -89,7 +78,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring)
regs[TM_CPPR] = cppr; regs[TM_CPPR] = cppr;
/* Reset the pending buffer bit */ /* Reset the pending buffer bit */
regs[TM_IPB] &= ~priority_to_ipb(cppr); regs[TM_IPB] &= ~xive_priority_to_ipb(cppr);
regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]); regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
/* Drop Exception bit */ /* Drop Exception bit */
@ -353,7 +342,7 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx, static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size) hwaddr offset, uint64_t value, unsigned size)
{ {
xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff)); xive_tctx_ipb_update(tctx, TM_QW1_OS, xive_priority_to_ipb(value & 0xff));
} }
static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk, static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
@ -1535,7 +1524,8 @@ bool xive_presenter_notify(XiveFabric *xfb, uint8_t format,
/* handle CPU exception delivery */ /* handle CPU exception delivery */
if (count) { if (count) {
trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring); trace_xive_presenter_notify(nvt_blk, nvt_idx, match.ring);
xive_tctx_ipb_update(match.tctx, match.ring, priority_to_ipb(priority)); xive_tctx_ipb_update(match.tctx, match.ring,
xive_priority_to_ipb(priority));
} }
return !!count; return !!count;
@ -1682,7 +1672,8 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
* use. The presenter will resend the interrupt when the vCPU * use. The presenter will resend the interrupt when the vCPU
* is dispatched again on a HW thread. * is dispatched again on a HW thread.
*/ */
ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) | priority_to_ipb(priority); ipb = xive_get_field32(NVT_W4_IPB, nvt.w4) |
xive_priority_to_ipb(priority);
nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb); nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, ipb);
xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4); xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);

11
include/hw/ppc/xive.h
View File

@ -458,6 +458,17 @@ struct XiveENDSource {
*/ */
#define XIVE_PRIORITY_MAX 7 #define XIVE_PRIORITY_MAX 7
/*
* Convert a priority number to an Interrupt Pending Buffer (IPB)
* register, which indicates a pending interrupt at the priority
* corresponding to the bit number
*/
static inline uint8_t xive_priority_to_ipb(uint8_t priority)
{
return priority > XIVE_PRIORITY_MAX ?
0 : 1 << (XIVE_PRIORITY_MAX - priority);
}
/* /*
* XIVE Thread Interrupt Management Aera (TIMA) * XIVE Thread Interrupt Management Aera (TIMA)
* *