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target-arm queue:

Browse Source 
* remove a line of redundant code
  * convert various TCG helper fns to use 'fpst' alias
  * Use float_status in helper_fcvtx_f64_to_f32
  * Use float_status in helper_vfp_fcvt{ds,sd}
  * Implement FEAT_XS
  * hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
  * tests/functional: update sbsa-ref firmware used in test
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Merge tag 'pull-target-arm-20241217' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * remove a line of redundant code
 * convert various TCG helper fns to use 'fpst' alias
 * Use float_status in helper_fcvtx_f64_to_f32
 * Use float_status in helper_vfp_fcvt{ds,sd}
 * Implement FEAT_XS
 * hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
 * tests/functional: update sbsa-ref firmware used in test

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# =Z/7q
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 17 Dec 2024 12:17:49 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241217' of https://git.linaro.org/people/pmaydell/qemu-arm:
  tests/functional: update sbsa-ref firmware used in test
  hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs
  tests/tcg/aarch64: add system test for FEAT_XS
  target/arm: Enable FEAT_XS for the max cpu
  target/arm: Add decodetree entry for DSB nXS variant
  target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns
  target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns
  target/arm: Implement fine-grained-trap handling for FEAT_XS
  target/arm: Use float_status in helper_vfp_fcvt{ds,sd}
  target/arm: Use float_status in helper_fcvtx_f64_to_f32
  target/arm: Convert neon_helper.c to use env alias
  target/arm: Convert vec_helper.c to use env alias
  target/arm: Convert sme_helper.c to fpst alias
  target/arm: Convert sve_helper.c to fpst alias
  target/arm: Convert neon_helper.c to fpst alias
  target/arm: Convert vec_helper.c to fpst alias
  target/arm: Convert helper-a64.c to fpst alias
  target/arm: Convert vfp_helper.c to fpst alias
  target/arm: remove redundant code

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2024-12-18 14:21:21 -05:00
commit 877fad2a3e
23 changed files with 1083 additions and 998 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
docs/system/arm/emulation.rst
View File

@ -154,6 +154,7 @@ the following architecture extensions:
- FEAT_VMID16 (16-bit VMID) - FEAT_VMID16 (16-bit VMID)
- FEAT_WFxT (WFE and WFI instructions with timeout) - FEAT_WFxT (WFE and WFI instructions with timeout)
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
- FEAT_XS (XS attribute)
For information on the specifics of these extensions, please refer For information on the specifics of these extensions, please refer
to the `Arm Architecture Reference Manual for A-profile architecture to the `Arm Architecture Reference Manual for A-profile architecture

44
hw/intc/arm_gicv3_its.c
View File

@ -465,7 +465,7 @@ static ItsCmdResult lookup_vte(GICv3ITSState *s, const char *who,
static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite, static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
int irqlevel) int irqlevel)
{ {
CTEntry cte; CTEntry cte = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
cmdres = lookup_cte(s, __func__, ite->icid, &cte); cmdres = lookup_cte(s, __func__, ite->icid, &cte);
@ -479,7 +479,7 @@ static ItsCmdResult process_its_cmd_phys(GICv3ITSState *s, const ITEntry *ite,
static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite, static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
int irqlevel) int irqlevel)
{ {
VTEntry vte; VTEntry vte = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
cmdres = lookup_vte(s, __func__, ite->vpeid, &vte); cmdres = lookup_vte(s, __func__, ite->vpeid, &vte);
@ -514,8 +514,8 @@ static ItsCmdResult process_its_cmd_virt(GICv3ITSState *s, const ITEntry *ite,
static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid, static ItsCmdResult do_process_its_cmd(GICv3ITSState *s, uint32_t devid,
uint32_t eventid, ItsCmdType cmd) uint32_t eventid, ItsCmdType cmd)
{ {
DTEntry dte; DTEntry dte = {};
ITEntry ite; ITEntry ite = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
int irqlevel; int irqlevel;
@ -583,8 +583,8 @@ static ItsCmdResult process_mapti(GICv3ITSState *s, const uint64_t *cmdpkt,
uint32_t pIntid = 0; uint32_t pIntid = 0;
uint64_t num_eventids; uint64_t num_eventids;
uint16_t icid = 0; uint16_t icid = 0;
DTEntry dte; DTEntry dte = {};
ITEntry ite; ITEntry ite = {};
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT; devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
eventid = cmdpkt[1] & EVENTID_MASK; eventid = cmdpkt[1] & EVENTID_MASK;
@ -651,8 +651,8 @@ static ItsCmdResult process_vmapti(GICv3ITSState *s, const uint64_t *cmdpkt,
{ {
uint32_t devid, eventid, vintid, doorbell, vpeid; uint32_t devid, eventid, vintid, doorbell, vpeid;
uint32_t num_eventids; uint32_t num_eventids;
DTEntry dte; DTEntry dte = {};
ITEntry ite; ITEntry ite = {};
if (!its_feature_virtual(s)) { if (!its_feature_virtual(s)) {
return CMD_CONTINUE; return CMD_CONTINUE;
@ -761,7 +761,7 @@ static bool update_cte(GICv3ITSState *s, uint16_t icid, const CTEntry *cte)
static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt) static ItsCmdResult process_mapc(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
uint16_t icid; uint16_t icid;
CTEntry cte; CTEntry cte = {};
icid = cmdpkt[2] & ICID_MASK; icid = cmdpkt[2] & ICID_MASK;
cte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK; cte.valid = cmdpkt[2] & CMD_FIELD_VALID_MASK;
@ -822,7 +822,7 @@ static bool update_dte(GICv3ITSState *s, uint32_t devid, const DTEntry *dte)
static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt) static ItsCmdResult process_mapd(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
uint32_t devid; uint32_t devid;
DTEntry dte; DTEntry dte = {};
devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT; devid = (cmdpkt[0] & DEVID_MASK) >> DEVID_SHIFT;
dte.size = cmdpkt[1] & SIZE_MASK; dte.size = cmdpkt[1] & SIZE_MASK;
@ -886,9 +886,9 @@ static ItsCmdResult process_movi(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
uint32_t devid, eventid; uint32_t devid, eventid;
uint16_t new_icid; uint16_t new_icid;
DTEntry dte; DTEntry dte = {};
CTEntry old_cte, new_cte; CTEntry old_cte = {}, new_cte = {};
ITEntry old_ite; ITEntry old_ite = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID); devid = FIELD_EX64(cmdpkt[0], MOVI_0, DEVICEID);
@ -965,7 +965,7 @@ static bool update_vte(GICv3ITSState *s, uint32_t vpeid, const VTEntry *vte)
static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt) static ItsCmdResult process_vmapp(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
VTEntry vte; VTEntry vte = {};
uint32_t vpeid; uint32_t vpeid;
if (!its_feature_virtual(s)) { if (!its_feature_virtual(s)) {
@ -1030,7 +1030,7 @@ static void vmovp_callback(gpointer data, gpointer opaque)
*/ */
GICv3ITSState *s = data; GICv3ITSState *s = data;
VmovpCallbackData *cbdata = opaque; VmovpCallbackData *cbdata = opaque;
VTEntry vte; VTEntry vte = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte); cmdres = lookup_vte(s, __func__, cbdata->vpeid, &vte);
@ -1085,9 +1085,9 @@ static ItsCmdResult process_vmovi(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
uint32_t devid, eventid, vpeid, doorbell; uint32_t devid, eventid, vpeid, doorbell;
bool doorbell_valid; bool doorbell_valid;
DTEntry dte; DTEntry dte = {};
ITEntry ite; ITEntry ite = {};
VTEntry old_vte, new_vte; VTEntry old_vte = {}, new_vte = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
if (!its_feature_virtual(s)) { if (!its_feature_virtual(s)) {
@ -1186,10 +1186,10 @@ static ItsCmdResult process_vinvall(GICv3ITSState *s, const uint64_t *cmdpkt)
static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt) static ItsCmdResult process_inv(GICv3ITSState *s, const uint64_t *cmdpkt)
{ {
uint32_t devid, eventid; uint32_t devid, eventid;
ITEntry ite; ITEntry ite = {};
DTEntry dte; DTEntry dte = {};
CTEntry cte; CTEntry cte = {};
VTEntry vte; VTEntry vte = {};
ItsCmdResult cmdres; ItsCmdResult cmdres;
devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID); devid = FIELD_EX64(cmdpkt[0], INV_0, DEVICEID);

80
target/arm/cpregs.h
View File

@ -126,6 +126,14 @@ enum {
* equivalent EL1 register when FEAT_NV2 is enabled. * equivalent EL1 register when FEAT_NV2 is enabled.
*/ */
ARM_CP_NV2_REDIRECT = 1 << 20, ARM_CP_NV2_REDIRECT = 1 << 20,
/*
* Flag: this is a TLBI insn which (when FEAT_XS is present) also has
* an NXS variant at the same encoding except that crn is 1 greater,
* so when registering this cpreg automatically also register one
* for the TLBI NXS variant. (For QEMU the NXS variant behaves
* identically to the normal one, other than FGT trapping handling.)
*/
ARM_CP_ADD_TLBI_NXS = 1 << 21,
}; };
/* /*
@ -621,6 +629,7 @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
FIELD(FGT, NXS, 13, 1) /* Honour HCR_EL2.FGTnXS to suppress FGT */
/* Which fine-grained trap bit register to check, if any */ /* Which fine-grained trap bit register to check, if any */
FIELD(FGT, TYPE, 10, 3) FIELD(FGT, TYPE, 10, 3)
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
@ -639,6 +648,17 @@ FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
#define DO_REV_BIT(REG, BITNAME) \ #define DO_REV_BIT(REG, BITNAME) \
FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
/*
* The FGT bits for TLBI maintenance instructions accessible at EL1 always
* affect the "normal" TLBI insns; they affect the corresponding TLBI insns
* with the nXS qualifier only if HCRX_EL2.FGTnXS is 0. We define e.g.
* FGT_TLBIVAE1 to use for the normal insn, and FGT_TLBIVAE1NXS to use
* for the nXS qualified insn.
*/
#define DO_TLBINXS_BIT(REG, BITNAME) \
FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT, \
FGT_##BITNAME##NXS = FGT_##BITNAME | R_FGT_NXS_MASK
typedef enum FGTBit { typedef enum FGTBit {
/* /*
* These bits tell us which register arrays to use: * These bits tell us which register arrays to use:
@ -772,36 +792,36 @@ typedef enum FGTBit {
DO_BIT(HFGITR, ATS1E0W), DO_BIT(HFGITR, ATS1E0W),
DO_BIT(HFGITR, ATS1E1RP), DO_BIT(HFGITR, ATS1E1RP),
DO_BIT(HFGITR, ATS1E1WP), DO_BIT(HFGITR, ATS1E1WP),
DO_BIT(HFGITR, TLBIVMALLE1OS), DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1OS),
DO_BIT(HFGITR, TLBIVAE1OS), DO_TLBINXS_BIT(HFGITR, TLBIVAE1OS),
DO_BIT(HFGITR, TLBIASIDE1OS), DO_TLBINXS_BIT(HFGITR, TLBIASIDE1OS),
DO_BIT(HFGITR, TLBIVAAE1OS), DO_TLBINXS_BIT(HFGITR, TLBIVAAE1OS),
DO_BIT(HFGITR, TLBIVALE1OS), DO_TLBINXS_BIT(HFGITR, TLBIVALE1OS),
DO_BIT(HFGITR, TLBIVAALE1OS), DO_TLBINXS_BIT(HFGITR, TLBIVAALE1OS),
DO_BIT(HFGITR, TLBIRVAE1OS), DO_TLBINXS_BIT(HFGITR, TLBIRVAE1OS),
DO_BIT(HFGITR, TLBIRVAAE1OS), DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1OS),
DO_BIT(HFGITR, TLBIRVALE1OS), DO_TLBINXS_BIT(HFGITR, TLBIRVALE1OS),
DO_BIT(HFGITR, TLBIRVAALE1OS), DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1OS),
DO_BIT(HFGITR, TLBIVMALLE1IS), DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1IS),
DO_BIT(HFGITR, TLBIVAE1IS), DO_TLBINXS_BIT(HFGITR, TLBIVAE1IS),
DO_BIT(HFGITR, TLBIASIDE1IS), DO_TLBINXS_BIT(HFGITR, TLBIASIDE1IS),
DO_BIT(HFGITR, TLBIVAAE1IS), DO_TLBINXS_BIT(HFGITR, TLBIVAAE1IS),
DO_BIT(HFGITR, TLBIVALE1IS), DO_TLBINXS_BIT(HFGITR, TLBIVALE1IS),
DO_BIT(HFGITR, TLBIVAALE1IS), DO_TLBINXS_BIT(HFGITR, TLBIVAALE1IS),
DO_BIT(HFGITR, TLBIRVAE1IS), DO_TLBINXS_BIT(HFGITR, TLBIRVAE1IS),
DO_BIT(HFGITR, TLBIRVAAE1IS), DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1IS),
DO_BIT(HFGITR, TLBIRVALE1IS), DO_TLBINXS_BIT(HFGITR, TLBIRVALE1IS),
DO_BIT(HFGITR, TLBIRVAALE1IS), DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1IS),
DO_BIT(HFGITR, TLBIRVAE1), DO_TLBINXS_BIT(HFGITR, TLBIRVAE1),
DO_BIT(HFGITR, TLBIRVAAE1), DO_TLBINXS_BIT(HFGITR, TLBIRVAAE1),
DO_BIT(HFGITR, TLBIRVALE1), DO_TLBINXS_BIT(HFGITR, TLBIRVALE1),
DO_BIT(HFGITR, TLBIRVAALE1), DO_TLBINXS_BIT(HFGITR, TLBIRVAALE1),
DO_BIT(HFGITR, TLBIVMALLE1), DO_TLBINXS_BIT(HFGITR, TLBIVMALLE1),
DO_BIT(HFGITR, TLBIVAE1), DO_TLBINXS_BIT(HFGITR, TLBIVAE1),
DO_BIT(HFGITR, TLBIASIDE1), DO_TLBINXS_BIT(HFGITR, TLBIASIDE1),
DO_BIT(HFGITR, TLBIVAAE1), DO_TLBINXS_BIT(HFGITR, TLBIVAAE1),
DO_BIT(HFGITR, TLBIVALE1), DO_TLBINXS_BIT(HFGITR, TLBIVALE1),
DO_BIT(HFGITR, TLBIVAALE1), DO_TLBINXS_BIT(HFGITR, TLBIVAALE1),
DO_BIT(HFGITR, CFPRCTX), DO_BIT(HFGITR, CFPRCTX),
DO_BIT(HFGITR, DVPRCTX), DO_BIT(HFGITR, DVPRCTX),
DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, CPPRCTX),

5
target/arm/cpu-features.h
View File

@ -474,6 +474,11 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
} }
static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
}
/* /*
* These are the values from APA/API/APA3. * These are the values from APA/API/APA3.
* In general these must be compared '>=', per the normal Arm ARM * In general these must be compared '>=', per the normal Arm ARM

30
target/arm/helper.c
View File

@ -5346,10 +5346,13 @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
} }
/* FEAT_CMOW adds CMOW */ /* FEAT_CMOW adds CMOW */
if (cpu_isar_feature(aa64_cmow, cpu)) { if (cpu_isar_feature(aa64_cmow, cpu)) {
valid_mask |= HCRX_CMOW; valid_mask |= HCRX_CMOW;
} }
/* FEAT_XS adds FGTnXS, FnXS */
if (cpu_isar_feature(aa64_xs, cpu)) {
valid_mask |= HCRX_FGTNXS | HCRX_FNXS;
}
/* Clear RES0 bits. */ /* Clear RES0 bits. */
env->cp15.hcrx_el2 = value & valid_mask; env->cp15.hcrx_el2 = value & valid_mask;
@ -9143,6 +9146,31 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
if (r->state != state && r->state != ARM_CP_STATE_BOTH) { if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
continue; continue;
} }
if ((r->type & ARM_CP_ADD_TLBI_NXS) &&
cpu_isar_feature(aa64_xs, cpu)) {
/*
* This is a TLBI insn which has an NXS variant. The
* NXS variant is at the same encoding except that
* crn is +1, and has the same behaviour except for
* fine-grained trapping. Add the NXS insn here and
* then fall through to add the normal register.
* add_cpreg_to_hashtable() copies the cpreg struct
* and name that it is passed, so it's OK to use
* a local struct here.
*/
ARMCPRegInfo nxs_ri = *r;
g_autofree char *name = g_strdup_printf("%sNXS", r->name);
assert(state == ARM_CP_STATE_AA64);
assert(nxs_ri.crn < 0xf);
nxs_ri.crn++;
if (nxs_ri.fgt) {
nxs_ri.fgt |= R_FGT_NXS_MASK;
}
add_cpreg_to_hashtable(cpu, &nxs_ri, opaque, state,
ARM_CP_SECSTATE_NS,
crm, opc1, opc2, name);
}
if (state == ARM_CP_STATE_AA32) { if (state == ARM_CP_STATE_AA32) {
/* /*
* Under AArch32 CP registers can be common * Under AArch32 CP registers can be common

638
target/arm/helper.h
View File

@ -109,33 +109,33 @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32)
DEF_HELPER_1(vfp_get_fpscr, i32, env) DEF_HELPER_1(vfp_get_fpscr, i32, env)
DEF_HELPER_2(vfp_set_fpscr, void, env, i32) DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_addh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr) DEF_HELPER_3(vfp_adds, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_addd, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_subh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr) DEF_HELPER_3(vfp_subs, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_subd, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_mulh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr) DEF_HELPER_3(vfp_muls, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr) DEF_HELPER_3(vfp_muld, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_divh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr) DEF_HELPER_3(vfp_divs, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_divd, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_maxh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr) DEF_HELPER_3(vfp_maxs, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_maxd, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_minh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr) DEF_HELPER_3(vfp_mins, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr) DEF_HELPER_3(vfp_mind, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr) DEF_HELPER_3(vfp_maxnums, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, fpst)
DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(vfp_minnumh, f16, f16, f16, fpst)
DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr) DEF_HELPER_3(vfp_minnums, f32, f32, f32, fpst)
DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr) DEF_HELPER_3(vfp_minnumd, f64, f64, f64, fpst)
DEF_HELPER_2(vfp_sqrth, f16, f16, ptr) DEF_HELPER_2(vfp_sqrth, f16, f16, fpst)
DEF_HELPER_2(vfp_sqrts, f32, f32, ptr) DEF_HELPER_2(vfp_sqrts, f32, f32, fpst)
DEF_HELPER_2(vfp_sqrtd, f64, f64, ptr) DEF_HELPER_2(vfp_sqrtd, f64, f64, fpst)
DEF_HELPER_3(vfp_cmph, void, f16, f16, env) DEF_HELPER_3(vfp_cmph, void, f16, f16, env)
DEF_HELPER_3(vfp_cmps, void, f32, f32, env) DEF_HELPER_3(vfp_cmps, void, f32, f32, env)
DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) DEF_HELPER_3(vfp_cmpd, void, f64, f64, env)
@ -143,112 +143,112 @@ DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env)
DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) DEF_HELPER_3(vfp_cmpes, void, f32, f32, env)
DEF_HELPER_3(vfp_cmped, void, f64, f64, env) DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtds, f64, f32, fpst)
DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, fpst)
DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, fpst)
DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, fpst)
DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitoh, f16, i32, fpst)
DEF_HELPER_2(vfp_uitos, f32, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, fpst)
DEF_HELPER_2(vfp_uitod, f64, i32, ptr) DEF_HELPER_2(vfp_uitod, f64, i32, fpst)
DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) DEF_HELPER_2(vfp_sitoh, f16, i32, fpst)
DEF_HELPER_2(vfp_sitos, f32, i32, ptr) DEF_HELPER_2(vfp_sitos, f32, i32, fpst)
DEF_HELPER_2(vfp_sitod, f64, i32, ptr) DEF_HELPER_2(vfp_sitod, f64, i32, fpst)
DEF_HELPER_2(vfp_touih, i32, f16, ptr) DEF_HELPER_2(vfp_touih, i32, f16, fpst)
DEF_HELPER_2(vfp_touis, i32, f32, ptr) DEF_HELPER_2(vfp_touis, i32, f32, fpst)
DEF_HELPER_2(vfp_touid, i32, f64, ptr) DEF_HELPER_2(vfp_touid, i32, f64, fpst)
DEF_HELPER_2(vfp_touizh, i32, f16, ptr) DEF_HELPER_2(vfp_touizh, i32, f16, fpst)
DEF_HELPER_2(vfp_touizs, i32, f32, ptr) DEF_HELPER_2(vfp_touizs, i32, f32, fpst)
DEF_HELPER_2(vfp_touizd, i32, f64, ptr) DEF_HELPER_2(vfp_touizd, i32, f64, fpst)
DEF_HELPER_2(vfp_tosih, s32, f16, ptr) DEF_HELPER_2(vfp_tosih, s32, f16, fpst)
DEF_HELPER_2(vfp_tosis, s32, f32, ptr) DEF_HELPER_2(vfp_tosis, s32, f32, fpst)
DEF_HELPER_2(vfp_tosid, s32, f64, ptr) DEF_HELPER_2(vfp_tosid, s32, f64, fpst)
DEF_HELPER_2(vfp_tosizh, s32, f16, ptr) DEF_HELPER_2(vfp_tosizh, s32, f16, fpst)
DEF_HELPER_2(vfp_tosizs, s32, f32, ptr) DEF_HELPER_2(vfp_tosizs, s32, f32, fpst)
DEF_HELPER_2(vfp_tosizd, s32, f64, ptr) DEF_HELPER_2(vfp_tosizd, s32, f64, fpst)
DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr) DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr) DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr) DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr) DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosqd_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touqd_round_to_zero, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_touhh, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshh, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toulh, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toslh, i32, f16, i32, fpst)
DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) DEF_HELPER_3(vfp_touqh, i64, f16, i32, fpst)
DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) DEF_HELPER_3(vfp_tosqh, i64, f16, i32, fpst)
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, fpst)
DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_touhs, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_touls, i32, f32, i32, fpst)
DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr) DEF_HELPER_3(vfp_touqs, i64, f32, i32, fpst)
DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr) DEF_HELPER_3(vfp_toshd, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosld, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosqd, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touqd, i64, f64, i32, fpst)
DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr) DEF_HELPER_3(vfp_shtos, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr) DEF_HELPER_3(vfp_sltos, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr) DEF_HELPER_3(vfp_sqtos, f32, i64, i32, fpst)
DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr) DEF_HELPER_3(vfp_uhtos, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr) DEF_HELPER_3(vfp_ultos, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr) DEF_HELPER_3(vfp_uqtos, f32, i64, i32, fpst)
DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_shtod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_sltod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_sqtod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uhtod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_shtoh, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_sltoh, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) DEF_HELPER_3(vfp_ultoh, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, fpst)
DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, fpst)
DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr) DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr) DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr) DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr) DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, fpst)
DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr) DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr) DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, fpst)
DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr) DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr) DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr) DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, fpst)
DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr) DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, fpst)
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, fpst)
DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32) DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, fpst, i32)
DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32) DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, fpst, i32)
DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32) DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, fpst, i32)
DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, fpst, i32)
DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, fpst)
DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, fpst)
DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
@ -258,15 +258,15 @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32)
DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32)
DEF_HELPER_3(ror_cc, i32, env, i32, i32) DEF_HELPER_3(ror_cc, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env)
DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, fpst)
DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32)
@ -310,34 +310,34 @@ DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32)
DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64)
DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64)
DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_sqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(neon_uqrshl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_uqshli_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_uqshli_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_uqshli_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_uqshli_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshlui_b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshlui_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshlui_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(neon_sqshlui_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_srshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_srshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@ -424,13 +424,13 @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, fpst)
DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_cge_f32, i32, i32, i32, fpst)
DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, fpst)
DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_acge_f32, i32, i32, i32, fpst)
DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, fpst)
DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) DEF_HELPER_3(neon_acge_f64, i64, i64, i64, fpst)
DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, fpst)
/* iwmmxt_helper.c */ /* iwmmxt_helper.c */
DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64)
@ -624,190 +624,190 @@ DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlah, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlah_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlas, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_uitos, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_tosszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_tosizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_touszh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vcvt_rm_uh, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vrint_rm_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vrint_rm_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vrintx_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcgt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcgt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcge0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcge0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fceq0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fceq0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcle0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fcle0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fclt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fclt0_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_fclt0_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fabd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fabd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fceq_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fceq_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fceq_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fcgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facge_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facge_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facge_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facgt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facgt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_facgt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnum_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmla_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmls_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmls_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfma_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfma_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfma_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfms_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfms_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_vfms_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmla_nf_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmls_nf_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
@ -859,18 +859,18 @@ DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
@ -1036,9 +1036,9 @@ DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@ -1058,9 +1058,9 @@ DEF_HELPER_FLAGS_6(gvec_bfmmla, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, env, i32) void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_sclamp_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
@ -1080,25 +1080,25 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_faddp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_faddp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_faddp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmaxnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnump_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnump_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fminnump_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_addp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_addp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

3
target/arm/tcg/a64.decode
View File

@ -260,6 +260,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
CLREX 1101 0101 0000 0011 0011 ---- 010 11111 CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
# domain bits.
DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111 SB 1101 0101 0000 0011 0011 0000 111 11111

1
target/arm/tcg/cpu64.c
View File

@ -1163,6 +1163,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 2); /* FEAT_BF16, FEAT_EBF16 */
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
cpu->isar.id_aa64isar1 = t; cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64isar2; t = cpu->isar.id_aa64isar2;

101
target/arm/tcg/helper-a64.c
View File

@ -130,40 +130,38 @@ static inline uint32_t float_rel_to_flags(int res)
return flags; return flags;
} }
uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status) uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, float_status *fp_status)
{ {
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
} }
uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status) uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, float_status *fp_status)
{ {
return float_rel_to_flags(float16_compare(x, y, fp_status)); return float_rel_to_flags(float16_compare(x, y, fp_status));
} }
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, float_status *fp_status)
{ {
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
} }
uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status) uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, float_status *fp_status)
{ {
return float_rel_to_flags(float32_compare(x, y, fp_status)); return float_rel_to_flags(float32_compare(x, y, fp_status));
} }
uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status) uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, float_status *fp_status)
{ {
return float_rel_to_flags(float64_compare_quiet(x, y, fp_status)); return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
} }
uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status) uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, float_status *fp_status)
{ {
return float_rel_to_flags(float64_compare(x, y, fp_status)); return float_rel_to_flags(float64_compare(x, y, fp_status));
} }
float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp) float32 HELPER(vfp_mulxs)(float32 a, float32 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float32_squash_input_denormal(a, fpst); a = float32_squash_input_denormal(a, fpst);
b = float32_squash_input_denormal(b, fpst); b = float32_squash_input_denormal(b, fpst);
@ -176,10 +174,8 @@ float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
return float32_mul(a, b, fpst); return float32_mul(a, b, fpst);
} }
float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp) float64 HELPER(vfp_mulxd)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float64_squash_input_denormal(a, fpst); a = float64_squash_input_denormal(a, fpst);
b = float64_squash_input_denormal(b, fpst); b = float64_squash_input_denormal(b, fpst);
@ -193,21 +189,18 @@ float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
} }
/* 64bit/double versions of the neon float compare functions */ /* 64bit/double versions of the neon float compare functions */
uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float64_eq_quiet(a, b, fpst); return -float64_eq_quiet(a, b, fpst);
} }
uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp) uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float64_le(b, a, fpst); return -float64_le(b, a, fpst);
} }
uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float64_lt(b, a, fpst); return -float64_lt(b, a, fpst);
} }
@ -216,10 +209,8 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
* multiply-add-and-halve. * multiply-add-and-halve.
*/ */
uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float16_squash_input_denormal(a, fpst); a = float16_squash_input_denormal(a, fpst);
b = float16_squash_input_denormal(b, fpst); b = float16_squash_input_denormal(b, fpst);
@ -231,10 +222,8 @@ uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
return float16_muladd(a, b, float16_two, 0, fpst); return float16_muladd(a, b, float16_two, 0, fpst);
} }
float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp) float32 HELPER(recpsf_f32)(float32 a, float32 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float32_squash_input_denormal(a, fpst); a = float32_squash_input_denormal(a, fpst);
b = float32_squash_input_denormal(b, fpst); b = float32_squash_input_denormal(b, fpst);
@ -246,10 +235,8 @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
return float32_muladd(a, b, float32_two, 0, fpst); return float32_muladd(a, b, float32_two, 0, fpst);
} }
float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp) float64 HELPER(recpsf_f64)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float64_squash_input_denormal(a, fpst); a = float64_squash_input_denormal(a, fpst);
b = float64_squash_input_denormal(b, fpst); b = float64_squash_input_denormal(b, fpst);
@ -261,10 +248,8 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
return float64_muladd(a, b, float64_two, 0, fpst); return float64_muladd(a, b, float64_two, 0, fpst);
} }
uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float16_squash_input_denormal(a, fpst); a = float16_squash_input_denormal(a, fpst);
b = float16_squash_input_denormal(b, fpst); b = float16_squash_input_denormal(b, fpst);
@ -276,10 +261,8 @@ uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst); return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst);
} }
float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp) float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float32_squash_input_denormal(a, fpst); a = float32_squash_input_denormal(a, fpst);
b = float32_squash_input_denormal(b, fpst); b = float32_squash_input_denormal(b, fpst);
@ -291,10 +274,8 @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst); return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
} }
float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp) float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float64_squash_input_denormal(a, fpst); a = float64_squash_input_denormal(a, fpst);
b = float64_squash_input_denormal(b, fpst); b = float64_squash_input_denormal(b, fpst);
@ -307,9 +288,8 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
} }
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) uint32_t HELPER(frecpx_f16)(uint32_t a, float_status *fpst)
{ {
float_status *fpst = fpstp;
uint16_t val16, sbit; uint16_t val16, sbit;
int16_t exp; int16_t exp;
@ -340,9 +320,8 @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
} }
} }
float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 HELPER(frecpx_f32)(float32 a, float_status *fpst)
{ {
float_status *fpst = fpstp;
uint32_t val32, sbit; uint32_t val32, sbit;
int32_t exp; int32_t exp;
@ -373,9 +352,8 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
} }
} }
float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 HELPER(frecpx_f64)(float64 a, float_status *fpst)
{ {
float_status *fpst = fpstp;
uint64_t val64, sbit; uint64_t val64, sbit;
int64_t exp; int64_t exp;
@ -406,10 +384,9 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
} }
} }
float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) float32 HELPER(fcvtx_f64_to_f32)(float64 a, float_status *fpst)
{ {
float32 r; float32 r;
float_status *fpst = &env->vfp.fp_status;
int old = get_float_rounding_mode(fpst); int old = get_float_rounding_mode(fpst);
set_float_rounding_mode(float_round_to_odd, fpst); set_float_rounding_mode(float_round_to_odd, fpst);
@ -453,9 +430,8 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
#define ADVSIMD_HALFOP(name) \ #define ADVSIMD_HALFOP(name) \
uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \ uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
return float16_ ## name(a, b, fpst); \ return float16_ ## name(a, b, fpst); \
} }
@ -469,11 +445,11 @@ ADVSIMD_HALFOP(minnum)
ADVSIMD_HALFOP(maxnum) ADVSIMD_HALFOP(maxnum)
#define ADVSIMD_TWOHALFOP(name) \ #define ADVSIMD_TWOHALFOP(name) \
uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \ uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, \
float_status *fpst) \
{ \ { \
float16 a1, a2, b1, b2; \ float16 a1, a2, b1, b2; \
uint32_t r1, r2; \ uint32_t r1, r2; \
float_status *fpst = fpstp; \
a1 = extract32(two_a, 0, 16); \ a1 = extract32(two_a, 0, 16); \
a2 = extract32(two_a, 16, 16); \ a2 = extract32(two_a, 16, 16); \
b1 = extract32(two_b, 0, 16); \ b1 = extract32(two_b, 0, 16); \
@ -493,10 +469,8 @@ ADVSIMD_TWOHALFOP(minnum)
ADVSIMD_TWOHALFOP(maxnum) ADVSIMD_TWOHALFOP(maxnum)
/* Data processing - scalar floating-point and advanced SIMD */ /* Data processing - scalar floating-point and advanced SIMD */
static float16 float16_mulx(float16 a, float16 b, void *fpstp) static float16 float16_mulx(float16 a, float16 b, float_status *fpst)
{ {
float_status *fpst = fpstp;
a = float16_squash_input_denormal(a, fpst); a = float16_squash_input_denormal(a, fpst);
b = float16_squash_input_denormal(b, fpst); b = float16_squash_input_denormal(b, fpst);
@ -514,16 +488,14 @@ ADVSIMD_TWOHALFOP(mulx)
/* fused multiply-accumulate */ /* fused multiply-accumulate */
uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c, uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
void *fpstp) float_status *fpst)
{ {
float_status *fpst = fpstp;
return float16_muladd(a, b, c, 0, fpst); return float16_muladd(a, b, c, 0, fpst);
} }
uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b, uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
uint32_t two_c, void *fpstp) uint32_t two_c, float_status *fpst)
{ {
float_status *fpst = fpstp;
float16 a1, a2, b1, b2, c1, c2; float16 a1, a2, b1, b2, c1, c2;
uint32_t r1, r2; uint32_t r1, r2;
a1 = extract32(two_a, 0, 16); a1 = extract32(two_a, 0, 16);
@ -545,31 +517,27 @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
int compare = float16_compare_quiet(a, b, fpst); int compare = float16_compare_quiet(a, b, fpst);
return ADVSIMD_CMPRES(compare == float_relation_equal); return ADVSIMD_CMPRES(compare == float_relation_equal);
} }
uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
int compare = float16_compare(a, b, fpst); int compare = float16_compare(a, b, fpst);
return ADVSIMD_CMPRES(compare == float_relation_greater || return ADVSIMD_CMPRES(compare == float_relation_greater ||
compare == float_relation_equal); compare == float_relation_equal);
} }
uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
int compare = float16_compare(a, b, fpst); int compare = float16_compare(a, b, fpst);
return ADVSIMD_CMPRES(compare == float_relation_greater); return ADVSIMD_CMPRES(compare == float_relation_greater);
} }
uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float16 f0 = float16_abs(a); float16 f0 = float16_abs(a);
float16 f1 = float16_abs(b); float16 f1 = float16_abs(b);
int compare = float16_compare(f0, f1, fpst); int compare = float16_compare(f0, f1, fpst);
@ -577,9 +545,8 @@ uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
compare == float_relation_equal); compare == float_relation_equal);
} }
uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float16 f0 = float16_abs(a); float16 f0 = float16_abs(a);
float16 f1 = float16_abs(b); float16 f1 = float16_abs(b);
int compare = float16_compare(f0, f1, fpst); int compare = float16_compare(f0, f1, fpst);
@ -587,12 +554,12 @@ uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
} }
/* round to integral */ /* round to integral */
uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status) uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, float_status *fp_status)
{ {
return float16_round_to_int(x, fp_status); return float16_round_to_int(x, fp_status);
} }
uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status) uint32_t HELPER(advsimd_rinth)(uint32_t x, float_status *fp_status)
{ {
int old_flags = get_float_exception_flags(fp_status), new_flags; int old_flags = get_float_exception_flags(fp_status), new_flags;
float16 ret; float16 ret;

116
target/arm/tcg/helper-a64.h
View File

@ -23,57 +23,57 @@ DEF_HELPER_2(msr_i_spsel, void, env, i32)
DEF_HELPER_2(msr_i_daifset, void, env, i32) DEF_HELPER_2(msr_i_daifset, void, env, i32)
DEF_HELPER_2(msr_i_daifclear, void, env, i32) DEF_HELPER_2(msr_i_daifclear, void, env, i32)
DEF_HELPER_1(msr_set_allint_el1, void, env) DEF_HELPER_1(msr_set_allint_el1, void, env)
DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, fpst)
DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, fpst)
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, fpst)
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, fpst)
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, fpst)
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, fpst)
DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(simd_tblx, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, fpst)
DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, fpst)
DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, fpst)
DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, fpst)
DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_addh, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_subh, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulh, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_divh, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, fpst)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, fpst)
DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, fpst)
DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_add2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_div2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_max2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_min2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, fpst)
DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, fpst)
DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, fpst)
DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth_exact, f16, f16, fpst)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, fpst)
DEF_HELPER_2(exception_return, void, env, i64) DEF_HELPER_2(exception_return, void, env, i64)
DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
@ -129,14 +129,14 @@ DEF_HELPER_4(cpyfe, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env) DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env)
DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)

4
target/arm/tcg/helper-sme.h
View File

@ -123,9 +123,9 @@ DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, env, i32) void, ptr, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sme_bfmopa, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, env, i32) void, ptr, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sme_smopa_s, TCG_CALL_NO_RWG,

426
target/arm/tcg/helper-sve.h
View File

@ -959,433 +959,433 @@ DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, ptr, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32) i64, i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32) i64, i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fadda_d, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, ptr, i32) i64, i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmge0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmge0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmge0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmgt0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmgt0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmgt0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmlt0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmlt0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmlt0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmle0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmle0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmle0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmeq0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmeq0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmeq0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmne0_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmne0_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcmne0_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadd_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadd_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsub_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsub_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsub_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmul_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmul_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmul_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fdiv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fdiv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fdiv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmin_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmin_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmin_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmax_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmax_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmax_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnum_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnum_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnum_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnum_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnum_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnum_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fabd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fabd_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fabd_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fscalbn_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fscalbn_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fscalbn_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmulx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i64, ptr, i32) void, ptr, ptr, ptr, i64, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_dh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_hs, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_hd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvt_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_bfcvt, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_hh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_hs, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_hs, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_ss, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_ss, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_hd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_hd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzs_dd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzs_dd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_hh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_hh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_hs, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_hs, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_ss, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_ss, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_hd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_hd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frecpx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frecpx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_frecpx_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_frecpx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fsqrt_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fsqrt_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fsqrt_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fsqrt_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fsqrt_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fsqrt_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmge_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmge_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmge_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmge_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmge_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmge_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmgt_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmgt_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmgt_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmgt_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmgt_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmgt_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmeq_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmeq_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmeq_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmeq_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmeq_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmeq_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmne_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmne_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmne_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmne_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmne_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmne_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmuo_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmuo_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmuo_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmuo_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcmuo_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcmuo_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facge_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facge_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facge_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facge_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facge_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facge_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facgt_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facgt_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facgt_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_facgt_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcadd_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcadd_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve_fcadd_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmla_zpzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fmls_zpzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmla_zpzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_7(sve_fcmla_zpzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve2_saddl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_saddl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_saddl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_saddl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@ -2582,39 +2582,39 @@ DEF_HELPER_FLAGS_4(sve2_xar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxnmp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminnmp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fmaxp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
@ -2682,8 +2682,8 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
@ -2755,20 +2755,20 @@ DEF_HELPER_FLAGS_5(sve2_cdot_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_bfcvtnt, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve2_sqshl_zpzi_b, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve2_sqshl_zpzi_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32) void, ptr, ptr, ptr, i32)

27
target/arm/tcg/neon_helper.c
View File

@ -130,11 +130,10 @@ void HELPER(name)(void *vd, void *vn, void *vm, uint32_t desc) \
} }
#define NEON_GVEC_VOP2_ENV(name, vtype) \ #define NEON_GVEC_VOP2_ENV(name, vtype) \
void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \ void HELPER(name)(void *vd, void *vn, void *vm, CPUARMState *env, uint32_t desc) \
{ \ { \
intptr_t i, opr_sz = simd_oprsz(desc); \ intptr_t i, opr_sz = simd_oprsz(desc); \
vtype *d = vd, *n = vn, *m = vm; \ vtype *d = vd, *n = vn, *m = vm; \
CPUARMState *env = venv; \
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \ for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
NEON_FN(d[i], n[i], m[i]); \ NEON_FN(d[i], n[i], m[i]); \
} \ } \
@ -142,12 +141,11 @@ void HELPER(name)(void *vd, void *vn, void *vm, void *venv, uint32_t desc) \
} }
#define NEON_GVEC_VOP2i_ENV(name, vtype) \ #define NEON_GVEC_VOP2i_ENV(name, vtype) \
void HELPER(name)(void *vd, void *vn, void *venv, uint32_t desc) \ void HELPER(name)(void *vd, void *vn, CPUARMState *env, uint32_t desc) \
{ \ { \
intptr_t i, opr_sz = simd_oprsz(desc); \ intptr_t i, opr_sz = simd_oprsz(desc); \
int imm = simd_data(desc); \ int imm = simd_data(desc); \
vtype *d = vd, *n = vn; \ vtype *d = vd, *n = vn; \
CPUARMState *env = venv; \
for (i = 0; i < opr_sz / sizeof(vtype); i++) { \ for (i = 0; i < opr_sz / sizeof(vtype); i++) { \
NEON_FN(d[i], n[i], imm); \ NEON_FN(d[i], n[i], imm); \
} \ } \
@ -1180,51 +1178,44 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do. * Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
* Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
*/ */
uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(neon_ceq_f32)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float32_eq_quiet(make_float32(a), make_float32(b), fpst); return -float32_eq_quiet(make_float32(a), make_float32(b), fpst);
} }
uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(neon_cge_f32)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float32_le(make_float32(b), make_float32(a), fpst); return -float32_le(make_float32(b), make_float32(a), fpst);
} }
uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(neon_cgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
return -float32_lt(make_float32(b), make_float32(a), fpst); return -float32_lt(make_float32(b), make_float32(a), fpst);
} }
uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(neon_acge_f32)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float32 f0 = float32_abs(make_float32(a)); float32 f0 = float32_abs(make_float32(a));
float32 f1 = float32_abs(make_float32(b)); float32 f1 = float32_abs(make_float32(b));
return -float32_le(f1, f0, fpst); return -float32_le(f1, f0, fpst);
} }
uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp) uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float32 f0 = float32_abs(make_float32(a)); float32 f0 = float32_abs(make_float32(a));
float32 f1 = float32_abs(make_float32(b)); float32 f1 = float32_abs(make_float32(b));
return -float32_lt(f1, f0, fpst); return -float32_lt(f1, f0, fpst);
} }
uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, void *fpstp) uint64_t HELPER(neon_acge_f64)(uint64_t a, uint64_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float64 f0 = float64_abs(make_float64(a)); float64 f0 = float64_abs(make_float64(a));
float64 f1 = float64_abs(make_float64(b)); float64 f1 = float64_abs(make_float64(b));
return -float64_le(f1, f0, fpst); return -float64_le(f1, f0, fpst);
} }
uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp) uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, float_status *fpst)
{ {
float_status *fpst = fpstp;
float64 f0 = float64_abs(make_float64(a)); float64 f0 = float64_abs(make_float64(a));
float64 f1 = float64_abs(make_float64(b)); float64 f1 = float64_abs(make_float64(b));
return -float64_lt(f1, f0, fpst); return -float64_lt(f1, f0, fpst);

9
target/arm/tcg/op_helper.c
View File

@ -817,6 +817,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX); unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS); unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
bool rev = FIELD_EX32(ri->fgt, FGT, REV); bool rev = FIELD_EX32(ri->fgt, FGT, REV);
bool nxs = FIELD_EX32(ri->fgt, FGT, NXS);
bool trapbit; bool trapbit;
if (ri->fgt & FGT_EXEC) { if (ri->fgt & FGT_EXEC) {
@ -830,7 +831,15 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
trapword = env->cp15.fgt_write[idx]; trapword = env->cp15.fgt_write[idx];
} }
if (nxs && (arm_hcrx_el2_eff(env) & HCRX_FGTNXS)) {
/*
* If HCRX_EL2.FGTnXS is 1 then the fine-grained trap for
* TLBI maintenance insns does *not* apply to the nXS variant.
*/
trapbit = 0;
} else {
trapbit = extract64(trapword, bitpos, 1); trapbit = extract64(trapword, bitpos, 1);
}
if (trapbit != rev) { if (trapbit != rev) {
res = CP_ACCESS_TRAP_EL2; res = CP_ACCESS_TRAP_EL2;
goto fail; goto fail;

8
target/arm/tcg/sme_helper.c
View File

@ -904,7 +904,7 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn,
} }
void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
void *vpm, void *vst, uint32_t desc) void *vpm, float_status *fpst_in, uint32_t desc)
{ {
intptr_t row, col, oprsz = simd_maxsz(desc); intptr_t row, col, oprsz = simd_maxsz(desc);
uint32_t neg = simd_data(desc) << 31; uint32_t neg = simd_data(desc) << 31;
@ -916,7 +916,7 @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
* update the cumulative fp exception status. It also produces * update the cumulative fp exception status. It also produces
* default nans. * default nans.
*/ */
fpst = *(float_status *)vst; fpst = *fpst_in;
set_default_nan_mode(true, &fpst); set_default_nan_mode(true, &fpst);
for (row = 0; row < oprsz; ) { for (row = 0; row < oprsz; ) {
@ -946,13 +946,13 @@ void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn,
} }
void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn,
void *vpm, void *vst, uint32_t desc) void *vpm, float_status *fpst_in, uint32_t desc)
{ {
intptr_t row, col, oprsz = simd_oprsz(desc) / 8; intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
uint64_t neg = (uint64_t)simd_data(desc) << 63; uint64_t neg = (uint64_t)simd_data(desc) << 63;
uint64_t *za = vza, *zn = vzn, *zm = vzm; uint64_t *za = vza, *zn = vzn, *zm = vzm;
uint8_t *pn = vpn, *pm = vpm; uint8_t *pn = vpn, *pm = vpm;
float_status fpst = *(float_status *)vst; float_status fpst = *fpst_in;
set_default_nan_mode(true, &fpst); set_default_nan_mode(true, &fpst);

96
target/arm/tcg/sve_helper.c
View File

@ -730,7 +730,7 @@ DO_ZPZZ_PAIR_D(sve2_sminp_zpzz_d, int64_t, DO_MIN)
#define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \ #define DO_ZPZZ_PAIR_FP(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
void *status, uint32_t desc) \ float_status *status, uint32_t desc) \
{ \ { \
intptr_t i, opr_sz = simd_oprsz(desc); \ intptr_t i, opr_sz = simd_oprsz(desc); \
for (i = 0; i < opr_sz; ) { \ for (i = 0; i < opr_sz; ) { \
@ -4190,7 +4190,7 @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
return TYPE##_##FUNC(lo, hi, status); \ return TYPE##_##FUNC(lo, hi, status); \
} \ } \
} \ } \
uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \ uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \
{ \ { \
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \ uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \ TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
@ -4205,7 +4205,7 @@ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
for (; i < maxsz; i += sizeof(TYPE)) { \ for (; i < maxsz; i += sizeof(TYPE)) { \
*(TYPE *)((void *)data + i) = IDENT; \ *(TYPE *)((void *)data + i) = IDENT; \
} \ } \
return NAME##_reduce(data, vs, maxsz / sizeof(TYPE)); \ return NAME##_reduce(data, s, maxsz / sizeof(TYPE)); \
} }
DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero) DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero)
@ -4232,7 +4232,7 @@ DO_REDUCE(sve_fmaxv_d, float64, H1_8, max, float64_chs(float64_infinity))
#undef DO_REDUCE #undef DO_REDUCE
uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg, uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc) float_status *status, uint32_t desc)
{ {
intptr_t i = 0, opr_sz = simd_oprsz(desc); intptr_t i = 0, opr_sz = simd_oprsz(desc);
float16 result = nn; float16 result = nn;
@ -4252,7 +4252,7 @@ uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
} }
uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg, uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc) float_status *status, uint32_t desc)
{ {
intptr_t i = 0, opr_sz = simd_oprsz(desc); intptr_t i = 0, opr_sz = simd_oprsz(desc);
float32 result = nn; float32 result = nn;
@ -4272,7 +4272,7 @@ uint64_t HELPER(sve_fadda_s)(uint64_t nn, void *vm, void *vg,
} }
uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg, uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
void *status, uint32_t desc) float_status *status, uint32_t desc)
{ {
intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8; intptr_t i = 0, opr_sz = simd_oprsz(desc) / 8;
uint64_t *m = vm; uint64_t *m = vm;
@ -4292,7 +4292,7 @@ uint64_t HELPER(sve_fadda_d)(uint64_t nn, void *vm, void *vg,
*/ */
#define DO_ZPZZ_FP(NAME, TYPE, H, OP) \ #define DO_ZPZZ_FP(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
void *status, uint32_t desc) \ float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc); \ intptr_t i = simd_oprsz(desc); \
uint64_t *g = vg; \ uint64_t *g = vg; \
@ -4381,7 +4381,7 @@ DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)
*/ */
#define DO_ZPZS_FP(NAME, TYPE, H, OP) \ #define DO_ZPZS_FP(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \ void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \
void *status, uint32_t desc) \ float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc); \ intptr_t i = simd_oprsz(desc); \
uint64_t *g = vg; \ uint64_t *g = vg; \
@ -4449,7 +4449,8 @@ DO_ZPZS_FP(sve_fmins_d, float64, H1_8, float64_min)
* With the extra float_status parameter. * With the extra float_status parameter.
*/ */
#define DO_ZPZ_FP(NAME, TYPE, H, OP) \ #define DO_ZPZ_FP(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vg, \
float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc); \ intptr_t i = simd_oprsz(desc); \
uint64_t *g = vg; \ uint64_t *g = vg; \
@ -4756,25 +4757,25 @@ static void do_fmla_zpzzz_h(void *vd, void *vn, void *vm, void *va, void *vg,
} }
void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0); do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0);
} }
void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0); do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0);
} }
void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000); do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0x8000, 0x8000);
} }
void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmls_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000); do_fmla_zpzzz_h(vd, vn, vm, va, vg, status, desc, 0, 0x8000);
} }
@ -4804,25 +4805,25 @@ static void do_fmla_zpzzz_s(void *vd, void *vn, void *vm, void *va, void *vg,
} }
void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0); do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0);
} }
void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0); do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0);
} }
void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000); do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0x80000000, 0x80000000);
} }
void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmls_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000); do_fmla_zpzzz_s(vd, vn, vm, va, vg, status, desc, 0, 0x80000000);
} }
@ -4852,25 +4853,25 @@ static void do_fmla_zpzzz_d(void *vd, void *vn, void *vm, void *va, void *vg,
} }
void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0); do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, 0);
} }
void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0); do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, 0);
} }
void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN); do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, INT64_MIN, INT64_MIN);
} }
void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN); do_fmla_zpzzz_d(vd, vn, vm, va, vg, status, desc, 0, INT64_MIN);
} }
@ -4882,7 +4883,7 @@ void HELPER(sve_fnmls_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
*/ */
#define DO_FPCMP_PPZZ(NAME, TYPE, H, OP) \ #define DO_FPCMP_PPZZ(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, \
void *status, uint32_t desc) \ float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \ intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
uint64_t *d = vd, *g = vg; \ uint64_t *d = vd, *g = vg; \
@ -4944,7 +4945,7 @@ DO_FPCMP_PPZZ_ALL(sve_facgt, DO_FACGT)
*/ */
#define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \ #define DO_FPCMP_PPZ0(NAME, TYPE, H, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, \ void HELPER(NAME)(void *vd, void *vn, void *vg, \
void *status, uint32_t desc) \ float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \ intptr_t i = simd_oprsz(desc), j = (i - 1) >> 6; \
uint64_t *d = vd, *g = vg; \ uint64_t *d = vd, *g = vg; \
@ -4982,7 +4983,8 @@ DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE)
/* FP Trig Multiply-Add. */ /* FP Trig Multiply-Add. */
void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm,
float_status *s, uint32_t desc)
{ {
static const float16 coeff[16] = { static const float16 coeff[16] = {
0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
@ -4998,11 +5000,12 @@ void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
mm = float16_abs(mm); mm = float16_abs(mm);
xx += 8; xx += 8;
} }
d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs); d[i] = float16_muladd(n[i], mm, coeff[xx], 0, s);
} }
} }
void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm,
float_status *s, uint32_t desc)
{ {
static const float32 coeff[16] = { static const float32 coeff[16] = {
0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9, 0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9,
@ -5020,11 +5023,12 @@ void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
mm = float32_abs(mm); mm = float32_abs(mm);
xx += 8; xx += 8;
} }
d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs); d[i] = float32_muladd(n[i], mm, coeff[xx], 0, s);
} }
} }
void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm,
float_status *s, uint32_t desc)
{ {
static const float64 coeff[16] = { static const float64 coeff[16] = {
0x3ff0000000000000ull, 0xbfc5555555555543ull, 0x3ff0000000000000ull, 0xbfc5555555555543ull,
@ -5046,7 +5050,7 @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
mm = float64_abs(mm); mm = float64_abs(mm);
xx += 8; xx += 8;
} }
d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs); d[i] = float64_muladd(n[i], mm, coeff[xx], 0, s);
} }
} }
@ -5055,7 +5059,7 @@ void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc)
*/ */
void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg, void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
void *vs, uint32_t desc) float_status *s, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
uint64_t *g = vg; uint64_t *g = vg;
@ -5077,17 +5081,17 @@ void HELPER(sve_fcadd_h)(void *vd, void *vn, void *vm, void *vg,
e3 = *(float16 *)(vm + H1_2(i)) ^ neg_imag; e3 = *(float16 *)(vm + H1_2(i)) ^ neg_imag;
if (likely((pg >> (i & 63)) & 1)) { if (likely((pg >> (i & 63)) & 1)) {
*(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, vs); *(float16 *)(vd + H1_2(i)) = float16_add(e0, e1, s);
} }
if (likely((pg >> (j & 63)) & 1)) { if (likely((pg >> (j & 63)) & 1)) {
*(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, vs); *(float16 *)(vd + H1_2(j)) = float16_add(e2, e3, s);
} }
} while (i & 63); } while (i & 63);
} while (i != 0); } while (i != 0);
} }
void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg, void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
void *vs, uint32_t desc) float_status *s, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
uint64_t *g = vg; uint64_t *g = vg;
@ -5109,17 +5113,17 @@ void HELPER(sve_fcadd_s)(void *vd, void *vn, void *vm, void *vg,
e3 = *(float32 *)(vm + H1_2(i)) ^ neg_imag; e3 = *(float32 *)(vm + H1_2(i)) ^ neg_imag;
if (likely((pg >> (i & 63)) & 1)) { if (likely((pg >> (i & 63)) & 1)) {
*(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, vs); *(float32 *)(vd + H1_2(i)) = float32_add(e0, e1, s);
} }
if (likely((pg >> (j & 63)) & 1)) { if (likely((pg >> (j & 63)) & 1)) {
*(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, vs); *(float32 *)(vd + H1_2(j)) = float32_add(e2, e3, s);
} }
} while (i & 63); } while (i & 63);
} while (i != 0); } while (i != 0);
} }
void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg, void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
void *vs, uint32_t desc) float_status *s, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
uint64_t *g = vg; uint64_t *g = vg;
@ -5141,10 +5145,10 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
e3 = *(float64 *)(vm + H1_2(i)) ^ neg_imag; e3 = *(float64 *)(vm + H1_2(i)) ^ neg_imag;
if (likely((pg >> (i & 63)) & 1)) { if (likely((pg >> (i & 63)) & 1)) {
*(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, vs); *(float64 *)(vd + H1_2(i)) = float64_add(e0, e1, s);
} }
if (likely((pg >> (j & 63)) & 1)) { if (likely((pg >> (j & 63)) & 1)) {
*(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, vs); *(float64 *)(vd + H1_2(j)) = float64_add(e2, e3, s);
} }
} while (i & 63); } while (i & 63);
} while (i != 0); } while (i != 0);
@ -5155,7 +5159,7 @@ void HELPER(sve_fcadd_d)(void *vd, void *vn, void *vm, void *vg,
*/ */
void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
unsigned rot = simd_data(desc); unsigned rot = simd_data(desc);
@ -5200,7 +5204,7 @@ void HELPER(sve_fcmla_zpzzz_h)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
unsigned rot = simd_data(desc); unsigned rot = simd_data(desc);
@ -5245,7 +5249,7 @@ void HELPER(sve_fcmla_zpzzz_s)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va, void HELPER(sve_fcmla_zpzzz_d)(void *vd, void *vn, void *vm, void *va,
void *vg, void *status, uint32_t desc) void *vg, float_status *status, uint32_t desc)
{ {
intptr_t j, i = simd_oprsz(desc); intptr_t j, i = simd_oprsz(desc);
unsigned rot = simd_data(desc); unsigned rot = simd_data(desc);
@ -7389,7 +7393,7 @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc)
} }
void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va, void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
void *status, uint32_t desc) float_status *status, uint32_t desc)
{ {
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4); intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float32) * 4);
@ -7427,7 +7431,7 @@ void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va, void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
void *status, uint32_t desc) float_status *status, uint32_t desc)
{ {
intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4); intptr_t s, opr_sz = simd_oprsz(desc) / (sizeof(float64) * 4);
@ -7463,7 +7467,8 @@ void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va,
} }
#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \ #define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vg, \
float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc); \ intptr_t i = simd_oprsz(desc); \
uint64_t *g = vg; \ uint64_t *g = vg; \
@ -7484,7 +7489,8 @@ DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float32) DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float32)
#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \ #define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vg, \
float_status *status, uint32_t desc) \
{ \ { \
intptr_t i = simd_oprsz(desc); \ intptr_t i = simd_oprsz(desc); \
uint64_t *g = vg; \ uint64_t *g = vg; \

202
target/arm/tcg/tlb-insns.c
View File

@ -617,95 +617,107 @@ static const ARMCPRegInfo tlbi_v8_cp_reginfo[] = {
/* AArch64 TLBI operations */ /* AArch64 TLBI operations */
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVMALLE1IS, .fgt = FGT_TLBIVMALLE1IS,
.writefn = tlbi_aa64_vmalle1is_write }, .writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAE1IS, .fgt = FGT_TLBIVAE1IS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIASIDE1IS, .fgt = FGT_TLBIASIDE1IS,
.writefn = tlbi_aa64_vmalle1is_write }, .writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAAE1IS, .fgt = FGT_TLBIVAAE1IS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVALE1IS, .fgt = FGT_TLBIVALE1IS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAALE1IS, .fgt = FGT_TLBIVAALE1IS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVMALLE1, .fgt = FGT_TLBIVMALLE1,
.writefn = tlbi_aa64_vmalle1_write }, .writefn = tlbi_aa64_vmalle1_write },
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAE1, .fgt = FGT_TLBIVAE1,
.writefn = tlbi_aa64_vae1_write }, .writefn = tlbi_aa64_vae1_write },
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIASIDE1, .fgt = FGT_TLBIASIDE1,
.writefn = tlbi_aa64_vmalle1_write }, .writefn = tlbi_aa64_vmalle1_write },
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAAE1, .fgt = FGT_TLBIVAAE1,
.writefn = tlbi_aa64_vae1_write }, .writefn = tlbi_aa64_vae1_write },
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVALE1, .fgt = FGT_TLBIVALE1,
.writefn = tlbi_aa64_vae1_write }, .writefn = tlbi_aa64_vae1_write },
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAALE1, .fgt = FGT_TLBIVAALE1,
.writefn = tlbi_aa64_vae1_write }, .writefn = tlbi_aa64_vae1_write },
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ipas2e1is_write }, .writefn = tlbi_aa64_ipas2e1is_write },
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ipas2e1is_write }, .writefn = tlbi_aa64_ipas2e1is_write },
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1is_write }, .writefn = tlbi_aa64_alle1is_write },
{ .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1is_write }, .writefn = tlbi_aa64_alle1is_write },
{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ipas2e1_write }, .writefn = tlbi_aa64_ipas2e1_write },
{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ipas2e1_write }, .writefn = tlbi_aa64_ipas2e1_write },
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1_write }, .writefn = tlbi_aa64_alle1_write },
{ .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1is_write }, .writefn = tlbi_aa64_alle1is_write },
}; };
@ -732,54 +744,60 @@ static const ARMCPRegInfo tlbi_el2_cp_reginfo[] = {
.writefn = tlbimva_hyp_is_write }, .writefn = tlbimva_hyp_is_write },
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_alle2_write }, .writefn = tlbi_aa64_alle2_write },
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2_write }, .writefn = tlbi_aa64_vae2_write },
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2_write }, .writefn = tlbi_aa64_vae2_write },
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_alle2is_write }, .writefn = tlbi_aa64_alle2is_write },
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2is_write }, .writefn = tlbi_aa64_vae2is_write },
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2is_write }, .writefn = tlbi_aa64_vae2is_write },
}; };
static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = { static const ARMCPRegInfo tlbi_el3_cp_reginfo[] = {
{ .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle3is_write }, .writefn = tlbi_aa64_alle3is_write },
{ .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3is_write }, .writefn = tlbi_aa64_vae3is_write },
{ .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3is_write }, .writefn = tlbi_aa64_vae3is_write },
{ .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle3_write }, .writefn = tlbi_aa64_alle3_write },
{ .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3_write }, .writefn = tlbi_aa64_vae3_write },
{ .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3_write }, .writefn = tlbi_aa64_vae3_write },
}; };
@ -981,204 +999,232 @@ static void tlbi_aa64_ripas2e1is_write(CPUARMState *env,
static const ARMCPRegInfo tlbirange_reginfo[] = { static const ARMCPRegInfo tlbirange_reginfo[] = {
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAE1IS, .fgt = FGT_TLBIRVAE1IS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAAE1IS, .fgt = FGT_TLBIRVAAE1IS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVALE1IS, .fgt = FGT_TLBIRVALE1IS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAALE1IS, .fgt = FGT_TLBIRVAALE1IS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAE1OS, .fgt = FGT_TLBIRVAE1OS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAAE1OS, .fgt = FGT_TLBIRVAAE1OS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVALE1OS, .fgt = FGT_TLBIRVALE1OS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAALE1OS, .fgt = FGT_TLBIRVAALE1OS,
.writefn = tlbi_aa64_rvae1is_write }, .writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAE1, .fgt = FGT_TLBIRVAE1,
.writefn = tlbi_aa64_rvae1_write }, .writefn = tlbi_aa64_rvae1_write },
{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAAE1, .fgt = FGT_TLBIRVAAE1,
.writefn = tlbi_aa64_rvae1_write }, .writefn = tlbi_aa64_rvae1_write },
{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVALE1, .fgt = FGT_TLBIRVALE1,
.writefn = tlbi_aa64_rvae1_write }, .writefn = tlbi_aa64_rvae1_write },
{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIRVAALE1, .fgt = FGT_TLBIRVAALE1,
.writefn = tlbi_aa64_rvae1_write }, .writefn = tlbi_aa64_rvae1_write },
{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ripas2e1is_write }, .writefn = tlbi_aa64_ripas2e1is_write },
{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ripas2e1is_write }, .writefn = tlbi_aa64_ripas2e1is_write },
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2is_write }, .writefn = tlbi_aa64_rvae2is_write },
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2is_write }, .writefn = tlbi_aa64_rvae2is_write },
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ripas2e1_write }, .writefn = tlbi_aa64_ripas2e1_write },
{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_ripas2e1_write }, .writefn = tlbi_aa64_ripas2e1_write },
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2is_write }, .writefn = tlbi_aa64_rvae2is_write },
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2is_write }, .writefn = tlbi_aa64_rvae2is_write },
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2_write }, .writefn = tlbi_aa64_rvae2_write },
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_rvae2_write }, .writefn = tlbi_aa64_rvae2_write },
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3is_write }, .writefn = tlbi_aa64_rvae3is_write },
{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3is_write }, .writefn = tlbi_aa64_rvae3is_write },
{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3is_write }, .writefn = tlbi_aa64_rvae3is_write },
{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3is_write }, .writefn = tlbi_aa64_rvae3is_write },
{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3_write }, .writefn = tlbi_aa64_rvae3_write },
{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_rvae3_write }, .writefn = tlbi_aa64_rvae3_write },
}; };
static const ARMCPRegInfo tlbios_reginfo[] = { static const ARMCPRegInfo tlbios_reginfo[] = {
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVMALLE1OS, .fgt = FGT_TLBIVMALLE1OS,
.writefn = tlbi_aa64_vmalle1is_write }, .writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
.fgt = FGT_TLBIVAE1OS, .fgt = FGT_TLBIVAE1OS,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIASIDE1OS, .fgt = FGT_TLBIASIDE1OS,
.writefn = tlbi_aa64_vmalle1is_write }, .writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAAE1OS, .fgt = FGT_TLBIVAAE1OS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVALE1OS, .fgt = FGT_TLBIVALE1OS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbos,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.fgt = FGT_TLBIVAALE1OS, .fgt = FGT_TLBIVAALE1OS,
.writefn = tlbi_aa64_vae1is_write }, .writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_alle2is_write }, .writefn = tlbi_aa64_alle2is_write },
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2is_write }, .writefn = tlbi_aa64_vae2is_write },
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1is_write }, .writefn = tlbi_aa64_alle1is_write },
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .access = PL2_W,
.type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS | ARM_CP_EL3_NO_EL2_UNDEF,
.writefn = tlbi_aa64_vae2is_write }, .writefn = tlbi_aa64_vae2is_write },
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW, .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle1is_write }, .writefn = tlbi_aa64_alle1is_write },
{ .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0,
.access = PL2_W, .type = ARM_CP_NOP }, .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3,
.access = PL2_W, .type = ARM_CP_NOP }, .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NOP }, .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7,
.access = PL2_W, .type = ARM_CP_NOP }, .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
{ .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_alle3is_write }, .writefn = tlbi_aa64_alle3is_write },
{ .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3is_write }, .writefn = tlbi_aa64_vae3is_write },
{ .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5,
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_ADD_TLBI_NXS,
.writefn = tlbi_aa64_vae3is_write }, .writefn = tlbi_aa64_vae3is_write },
}; };

26
target/arm/tcg/translate-a64.c
View File

@ -1986,6 +1986,15 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
return true; return true;
} }
static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
{
if (!dc_isar_feature(aa64_xs, s)) {
return false;
}
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
return true;
}
static bool trans_ISB(DisasContext *s, arg_ISB *a) static bool trans_ISB(DisasContext *s, arg_ISB *a)
{ {
/* /*
@ -8502,8 +8511,9 @@ static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) { if (fp_access_check(s)) {
TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn); TCGv_i32 tcg_rn = read_fp_sreg(s, a->rn);
TCGv_i64 tcg_rd = tcg_temp_new_i64(); TCGv_i64 tcg_rd = tcg_temp_new_i64();
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env); gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, fpst);
write_fp_dreg(s, a->rd, tcg_rd); write_fp_dreg(s, a->rd, tcg_rd);
} }
return true; return true;
@ -8528,8 +8538,9 @@ static bool trans_FCVT_s_sd(DisasContext *s, arg_rr *a)
if (fp_access_check(s)) { if (fp_access_check(s)) {
TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn); TCGv_i64 tcg_rn = read_fp_dreg(s, a->rn);
TCGv_i32 tcg_rd = tcg_temp_new_i32(); TCGv_i32 tcg_rd = tcg_temp_new_i32();
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env); gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, fpst);
write_fp_sreg(s, a->rd, tcg_rd); write_fp_sreg(s, a->rd, tcg_rd);
} }
return true; return true;
@ -9102,7 +9113,7 @@ static void gen_fcvtxn_sd(TCGv_i64 d, TCGv_i64 n)
* with von Neumann rounding (round to odd) * with von Neumann rounding (round to odd)
*/ */
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
gen_helper_fcvtx_f64_to_f32(tmp, n, tcg_env); gen_helper_fcvtx_f64_to_f32(tmp, n, fpstatus_ptr(FPST_FPCR));
tcg_gen_extu_i32_i64(d, tmp); tcg_gen_extu_i32_i64(d, tmp);
} }
@ -9208,7 +9219,9 @@ static void gen_fcvtn_hs(TCGv_i64 d, TCGv_i64 n)
static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n) static void gen_fcvtn_sd(TCGv_i64 d, TCGv_i64 n)
{ {
TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp = tcg_temp_new_i32();
gen_helper_vfp_fcvtsd(tmp, n, tcg_env); TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
gen_helper_vfp_fcvtsd(tmp, n, fpst);
tcg_gen_extu_i32_i64(d, tmp); tcg_gen_extu_i32_i64(d, tmp);
} }
@ -9490,11 +9503,13 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
* The only instruction like this is FCVTL. * The only instruction like this is FCVTL.
*/ */
int pass; int pass;
TCGv_ptr fpst;
if (!fp_access_check(s)) { if (!fp_access_check(s)) {
return true; return true;
} }
fpst = fpstatus_ptr(FPST_FPCR);
if (a->esz == MO_64) { if (a->esz == MO_64) {
/* 32 -> 64 bit fp conversion */ /* 32 -> 64 bit fp conversion */
TCGv_i64 tcg_res[2]; TCGv_i64 tcg_res[2];
@ -9504,7 +9519,7 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
for (pass = 0; pass < 2; pass++) { for (pass = 0; pass < 2; pass++) {
tcg_res[pass] = tcg_temp_new_i64(); tcg_res[pass] = tcg_temp_new_i64();
read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32); read_vec_element_i32(s, tcg_op, a->rn, srcelt + pass, MO_32);
gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env); gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, fpst);
} }
for (pass = 0; pass < 2; pass++) { for (pass = 0; pass < 2; pass++) {
write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64); write_vec_element(s, tcg_res[pass], a->rd, pass, MO_64);
@ -9513,7 +9528,6 @@ static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
/* 16 -> 32 bit fp conversion */ /* 16 -> 32 bit fp conversion */
int srcelt = a->q ? 4 : 0; int srcelt = a->q ? 4 : 0;
TCGv_i32 tcg_res[4]; TCGv_i32 tcg_res[4];
TCGv_ptr fpst = fpstatus_ptr(FPST_FPCR);
TCGv_i32 ahp = get_ahp_flag(); TCGv_i32 ahp = get_ahp_flag();
for (pass = 0; pass < 4; pass++) { for (pass = 0; pass < 4; pass++) {

4
target/arm/tcg/translate-vfp.c
View File

@ -2937,7 +2937,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
vm = tcg_temp_new_i32(); vm = tcg_temp_new_i32();
vd = tcg_temp_new_i64(); vd = tcg_temp_new_i64();
vfp_load_reg32(vm, a->vm); vfp_load_reg32(vm, a->vm);
gen_helper_vfp_fcvtds(vd, vm, tcg_env); gen_helper_vfp_fcvtds(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg64(vd, a->vd); vfp_store_reg64(vd, a->vd);
return true; return true;
} }
@ -2963,7 +2963,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
vd = tcg_temp_new_i32(); vd = tcg_temp_new_i32();
vm = tcg_temp_new_i64(); vm = tcg_temp_new_i64();
vfp_load_reg64(vm, a->vm); vfp_load_reg64(vm, a->vm);
gen_helper_vfp_fcvtsd(vd, vm, tcg_env); gen_helper_vfp_fcvtsd(vd, vm, fpstatus_ptr(FPST_FPCR));
vfp_store_reg32(vd, a->vd); vfp_store_reg32(vd, a->vd);
return true; return true;
} }

79
target/arm/tcg/vec_helper.c
View File

@ -873,13 +873,12 @@ DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, H8)
DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8) DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8)
void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float16 *d = vd; float16 *d = vd;
float16 *n = vn; float16 *n = vn;
float16 *m = vm; float16 *m = vm;
float_status *fpst = vfpst;
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = neg_real ^ 1; uint32_t neg_imag = neg_real ^ 1;
uintptr_t i; uintptr_t i;
@ -901,13 +900,12 @@ void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
} }
void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm, void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float32 *d = vd; float32 *d = vd;
float32 *n = vn; float32 *n = vn;
float32 *m = vm; float32 *m = vm;
float_status *fpst = vfpst;
uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1); uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = neg_real ^ 1; uint32_t neg_imag = neg_real ^ 1;
uintptr_t i; uintptr_t i;
@ -929,13 +927,12 @@ void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
} }
void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm, void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float64 *d = vd; float64 *d = vd;
float64 *n = vn; float64 *n = vn;
float64 *m = vm; float64 *m = vm;
float_status *fpst = vfpst;
uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1); uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
uint64_t neg_imag = neg_real ^ 1; uint64_t neg_imag = neg_real ^ 1;
uintptr_t i; uintptr_t i;
@ -957,11 +954,10 @@ void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
} }
void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float16 *d = vd, *n = vn, *m = vm, *a = va; float16 *d = vd, *n = vn, *m = vm, *a = va;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint32_t neg_real = flip ^ neg_imag; uint32_t neg_real = flip ^ neg_imag;
@ -984,11 +980,10 @@ void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float16 *d = vd, *n = vn, *m = vm, *a = va; float16 *d = vd, *n = vn, *m = vm, *a = va;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
@ -1019,11 +1014,10 @@ void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float32 *d = vd, *n = vn, *m = vm, *a = va; float32 *d = vd, *n = vn, *m = vm, *a = va;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint32_t neg_real = flip ^ neg_imag; uint32_t neg_real = flip ^ neg_imag;
@ -1046,11 +1040,10 @@ void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float32 *d = vd, *n = vn, *m = vm, *a = va; float32 *d = vd, *n = vn, *m = vm, *a = va;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2); intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
@ -1081,11 +1074,10 @@ void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, void *va,
void *vfpst, uint32_t desc) float_status *fpst, uint32_t desc)
{ {
uintptr_t opr_sz = simd_oprsz(desc); uintptr_t opr_sz = simd_oprsz(desc);
float64 *d = vd, *n = vn, *m = vm, *a = va; float64 *d = vd, *n = vn, *m = vm, *a = va;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1); uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint64_t neg_real = flip ^ neg_imag; uint64_t neg_real = flip ^ neg_imag;
@ -1187,9 +1179,8 @@ static uint64_t float64_acgt(float64 op1, float64 op2, float_status *stat)
return -float64_lt(float64_abs(op2), float64_abs(op1), stat); return -float64_lt(float64_abs(op2), float64_abs(op1), stat);
} }
static int16_t vfp_tosszh(float16 x, void *fpstp) static int16_t vfp_tosszh(float16 x, float_status *fpst)
{ {
float_status *fpst = fpstp;
if (float16_is_any_nan(x)) { if (float16_is_any_nan(x)) {
float_raise(float_flag_invalid, fpst); float_raise(float_flag_invalid, fpst);
return 0; return 0;
@ -1197,9 +1188,8 @@ static int16_t vfp_tosszh(float16 x, void *fpstp)
return float16_to_int16_round_to_zero(x, fpst); return float16_to_int16_round_to_zero(x, fpst);
} }
static uint16_t vfp_touszh(float16 x, void *fpstp) static uint16_t vfp_touszh(float16 x, float_status *fpst)
{ {
float_status *fpst = fpstp;
if (float16_is_any_nan(x)) { if (float16_is_any_nan(x)) {
float_raise(float_flag_invalid, fpst); float_raise(float_flag_invalid, fpst);
return 0; return 0;
@ -1208,7 +1198,7 @@ static uint16_t vfp_touszh(float16 x, void *fpstp)
} }
#define DO_2OP(NAME, FUNC, TYPE) \ #define DO_2OP(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
TYPE *d = vd, *n = vn; \ TYPE *d = vd, *n = vn; \
@ -1368,7 +1358,8 @@ static float32 float32_rsqrts_nf(float32 op1, float32 op2, float_status *stat)
} }
#define DO_3OP(NAME, FUNC, TYPE) \ #define DO_3OP(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vm, \
float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
TYPE *d = vd, *n = vn, *m = vm; \ TYPE *d = vd, *n = vn, *m = vm; \
@ -1523,7 +1514,8 @@ static float64 float64_mulsub_f(float64 dest, float64 op1, float64 op2,
} }
#define DO_MULADD(NAME, FUNC, TYPE) \ #define DO_MULADD(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vm, \
float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
TYPE *d = vd, *n = vn, *m = vm; \ TYPE *d = vd, *n = vn, *m = vm; \
@ -1600,7 +1592,8 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8)
#undef DO_MLA_IDX #undef DO_MLA_IDX
#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \ #define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vm, \
float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, j, oprsz = simd_oprsz(desc); \ intptr_t i, j, oprsz = simd_oprsz(desc); \
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \ intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
@ -1644,7 +1637,7 @@ DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4)
#define DO_FMLA_IDX(NAME, TYPE, H) \ #define DO_FMLA_IDX(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
void *stat, uint32_t desc) \ float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, j, oprsz = simd_oprsz(desc); \ intptr_t i, j, oprsz = simd_oprsz(desc); \
intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \ intptr_t segment = MIN(16, oprsz) / sizeof(TYPE); \
@ -2064,28 +2057,25 @@ static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
} }
void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
CPUARMState *env = venv;
do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc, do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
} }
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
CPUARMState *env = venv;
do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc, do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
} }
void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void *vm, void *va,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
intptr_t i, oprsz = simd_oprsz(desc); intptr_t i, oprsz = simd_oprsz(desc);
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15; uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
CPUARMState *env = venv;
float_status *status = &env->vfp.fp_status; float_status *status = &env->vfp.fp_status;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16); bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
@ -2129,29 +2119,26 @@ static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
} }
void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
CPUARMState *env = venv;
do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc, do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
} }
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm, void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
CPUARMState *env = venv;
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
} }
void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va, void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void *vm, void *va,
void *venv, uint32_t desc) CPUARMState *env, uint32_t desc)
{ {
intptr_t i, j, oprsz = simd_oprsz(desc); intptr_t i, j, oprsz = simd_oprsz(desc);
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15; uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16); intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16); intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
CPUARMState *env = venv;
float_status *status = &env->vfp.fp_status; float_status *status = &env->vfp.fp_status;
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16); bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status_f16);
@ -2410,7 +2397,8 @@ DO_ABA(gvec_uaba_d, uint64_t)
#undef DO_ABA #undef DO_ABA
#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ #define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, void *vm, \
float_status *stat, uint32_t desc) \
{ \ { \
ARMVectorReg scratch; \ ARMVectorReg scratch; \
intptr_t oprsz = simd_oprsz(desc); \ intptr_t oprsz = simd_oprsz(desc); \
@ -2495,7 +2483,7 @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
#undef DO_3OP_PAIR #undef DO_3OP_PAIR
#define DO_VCVT_FIXED(NAME, FUNC, TYPE) \ #define DO_VCVT_FIXED(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
{ \ { \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
int shift = simd_data(desc); \ int shift = simd_data(desc); \
@ -2524,9 +2512,8 @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
#undef DO_VCVT_FIXED #undef DO_VCVT_FIXED
#define DO_VCVT_RMODE(NAME, FUNC, TYPE) \ #define DO_VCVT_RMODE(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
{ \ { \
float_status *fpst = stat; \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
uint32_t rmode = simd_data(desc); \ uint32_t rmode = simd_data(desc); \
uint32_t prev_rmode = get_float_rounding_mode(fpst); \ uint32_t prev_rmode = get_float_rounding_mode(fpst); \
@ -2549,9 +2536,8 @@ DO_VCVT_RMODE(gvec_vcvt_rm_uh, helper_vfp_touhh, uint16_t)
#undef DO_VCVT_RMODE #undef DO_VCVT_RMODE
#define DO_VRINT_RMODE(NAME, FUNC, TYPE) \ #define DO_VRINT_RMODE(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ void HELPER(NAME)(void *vd, void *vn, float_status *fpst, uint32_t desc) \
{ \ { \
float_status *fpst = stat; \
intptr_t i, oprsz = simd_oprsz(desc); \ intptr_t i, oprsz = simd_oprsz(desc); \
uint32_t rmode = simd_data(desc); \ uint32_t rmode = simd_data(desc); \
uint32_t prev_rmode = get_float_rounding_mode(fpst); \ uint32_t prev_rmode = get_float_rounding_mode(fpst); \
@ -2570,10 +2556,9 @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32_t)
#undef DO_VRINT_RMODE #undef DO_VRINT_RMODE
#ifdef TARGET_AARCH64 #ifdef TARGET_AARCH64
void HELPER(simd_tblx)(void *vd, void *vm, void *venv, uint32_t desc) void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)
{ {
const uint8_t *indices = vm; const uint8_t *indices = vm;
CPUARMState *env = venv;
size_t oprsz = simd_oprsz(desc); size_t oprsz = simd_oprsz(desc);
uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5); uint32_t rn = extract32(desc, SIMD_DATA_SHIFT, 5);
bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1); bool is_tbx = extract32(desc, SIMD_DATA_SHIFT + 5, 1);
@ -3015,7 +3000,7 @@ void HELPER(gvec_bfmmla)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va, void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
void *stat, uint32_t desc) float_status *stat, uint32_t desc)
{ {
intptr_t i, opr_sz = simd_oprsz(desc); intptr_t i, opr_sz = simd_oprsz(desc);
intptr_t sel = simd_data(desc); intptr_t sel = simd_data(desc);
@ -3031,7 +3016,7 @@ void HELPER(gvec_bfmlal)(void *vd, void *vn, void *vm, void *va,
} }
void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm, void HELPER(gvec_bfmlal_idx)(void *vd, void *vn, void *vm,
void *va, void *stat, uint32_t desc) void *va, float_status *stat, uint32_t desc)
{ {
intptr_t i, j, opr_sz = simd_oprsz(desc); intptr_t i, j, opr_sz = simd_oprsz(desc);
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT, 1); intptr_t sel = extract32(desc, SIMD_DATA_SHIFT, 1);

130
target/arm/vfp_helper.c
View File

@ -289,19 +289,16 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val)
#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
#define VFP_BINOP(name) \ #define VFP_BINOP(name) \
dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
return float16_ ## name(a, b, fpst); \ return float16_ ## name(a, b, fpst); \
} \ } \
float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ float32 VFP_HELPER(name, s)(float32 a, float32 b, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
return float32_ ## name(a, b, fpst); \ return float32_ ## name(a, b, fpst); \
} \ } \
float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ float64 VFP_HELPER(name, d)(float64 a, float64 b, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
return float64_ ## name(a, b, fpst); \ return float64_ ## name(a, b, fpst); \
} }
VFP_BINOP(add) VFP_BINOP(add)
@ -314,19 +311,19 @@ VFP_BINOP(minnum)
VFP_BINOP(maxnum) VFP_BINOP(maxnum)
#undef VFP_BINOP #undef VFP_BINOP
dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, void *fpstp) dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, float_status *fpst)
{ {
return float16_sqrt(a, fpstp); return float16_sqrt(a, fpst);
} }
float32 VFP_HELPER(sqrt, s)(float32 a, void *fpstp) float32 VFP_HELPER(sqrt, s)(float32 a, float_status *fpst)
{ {
return float32_sqrt(a, fpstp); return float32_sqrt(a, fpst);
} }
float64 VFP_HELPER(sqrt, d)(float64 a, void *fpstp) float64 VFP_HELPER(sqrt, d)(float64 a, float_status *fpst)
{ {
return float64_sqrt(a, fpstp); return float64_sqrt(a, fpst);
} }
static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
@ -371,16 +368,14 @@ DO_VFP_cmp(d, float64, float64, fp_status)
/* Integer to float and float to integer conversions */ /* Integer to float and float to integer conversions */
#define CONV_ITOF(name, ftype, fsz, sign) \ #define CONV_ITOF(name, ftype, fsz, sign) \
ftype HELPER(name)(uint32_t x, void *fpstp) \ ftype HELPER(name)(uint32_t x, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
} }
#define CONV_FTOI(name, ftype, fsz, sign, round) \ #define CONV_FTOI(name, ftype, fsz, sign, round) \
sign##int32_t HELPER(name)(ftype x, void *fpstp) \ sign##int32_t HELPER(name)(ftype x, float_status *fpst) \
{ \ { \
float_status *fpst = fpstp; \
if (float##fsz##_is_any_nan(x)) { \ if (float##fsz##_is_any_nan(x)) { \
float_raise(float_flag_invalid, fpst); \ float_raise(float_flag_invalid, fpst); \
return 0; \ return 0; \
@ -405,22 +400,22 @@ FLOAT_CONVS(ui, d, float64, 64, u)
#undef FLOAT_CONVS #undef FLOAT_CONVS
/* floating point conversion */ /* floating point conversion */
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status)
{ {
return float32_to_float64(x, &env->vfp.fp_status); return float32_to_float64(x, status);
} }
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status)
{ {
return float64_to_float32(x, &env->vfp.fp_status); return float64_to_float32(x, status);
} }
uint32_t HELPER(bfcvt)(float32 x, void *status) uint32_t HELPER(bfcvt)(float32 x, float_status *status)
{ {
return float32_to_bfloat16(x, status); return float32_to_bfloat16(x, status);
} }
uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) uint32_t HELPER(bfcvt_pair)(uint64_t pair, float_status *status)
{ {
bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status);
bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status);
@ -436,26 +431,25 @@ uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status)
*/ */
#define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
void *fpstp) \ float_status *fpst) \
{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } { return itype##_to_##float##fsz##_scalbn(x, -shift, fpst); }
#define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
uint32_t shift, \ uint32_t shift, \
void *fpstp) \ float_status *fpst) \
{ \ { \
ftype ret; \ ftype ret; \
float_status *fpst = fpstp; \
FloatRoundMode oldmode = fpst->float_rounding_mode; \ FloatRoundMode oldmode = fpst->float_rounding_mode; \
fpst->float_rounding_mode = float_round_nearest_even; \ fpst->float_rounding_mode = float_round_nearest_even; \
ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \ ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpst); \
fpst->float_rounding_mode = oldmode; \ fpst->float_rounding_mode = oldmode; \
return ret; \ return ret; \
} }
#define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
void *fpst) \ float_status *fpst) \
{ \ { \
if (unlikely(float##fsz##_is_any_nan(x))) { \ if (unlikely(float##fsz##_is_any_nan(x))) { \
float_raise(float_flag_invalid, fpst); \ float_raise(float_flag_invalid, fpst); \
@ -508,10 +502,8 @@ VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64,
/* Set the current fp rounding mode and return the old one. /* Set the current fp rounding mode and return the old one.
* The argument is a softfloat float_round_ value. * The argument is a softfloat float_round_ value.
*/ */
uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) uint32_t HELPER(set_rmode)(uint32_t rmode, float_status *fp_status)
{ {
float_status *fp_status = fpstp;
uint32_t prev_rmode = get_float_rounding_mode(fp_status); uint32_t prev_rmode = get_float_rounding_mode(fp_status);
set_float_rounding_mode(rmode, fp_status); set_float_rounding_mode(rmode, fp_status);
@ -519,12 +511,12 @@ uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
} }
/* Half precision conversions. */ /* Half precision conversions. */
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, float_status *fpst,
uint32_t ahp_mode)
{ {
/* Squash FZ16 to 0 for the duration of conversion. In this case, /* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing input denormals. * it would affect flushing input denormals.
*/ */
float_status *fpst = fpstp;
bool save = get_flush_inputs_to_zero(fpst); bool save = get_flush_inputs_to_zero(fpst);
set_flush_inputs_to_zero(false, fpst); set_flush_inputs_to_zero(false, fpst);
float32 r = float16_to_float32(a, !ahp_mode, fpst); float32 r = float16_to_float32(a, !ahp_mode, fpst);
@ -532,12 +524,12 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
return r; return r;
} }
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, float_status *fpst,
uint32_t ahp_mode)
{ {
/* Squash FZ16 to 0 for the duration of conversion. In this case, /* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing output denormals. * it would affect flushing output denormals.
*/ */
float_status *fpst = fpstp;
bool save = get_flush_to_zero(fpst); bool save = get_flush_to_zero(fpst);
set_flush_to_zero(false, fpst); set_flush_to_zero(false, fpst);
float16 r = float32_to_float16(a, !ahp_mode, fpst); float16 r = float32_to_float16(a, !ahp_mode, fpst);
@ -545,12 +537,12 @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
return r; return r;
} }
float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, float_status *fpst,
uint32_t ahp_mode)
{ {
/* Squash FZ16 to 0 for the duration of conversion. In this case, /* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing input denormals. * it would affect flushing input denormals.
*/ */
float_status *fpst = fpstp;
bool save = get_flush_inputs_to_zero(fpst); bool save = get_flush_inputs_to_zero(fpst);
set_flush_inputs_to_zero(false, fpst); set_flush_inputs_to_zero(false, fpst);
float64 r = float16_to_float64(a, !ahp_mode, fpst); float64 r = float16_to_float64(a, !ahp_mode, fpst);
@ -558,12 +550,12 @@ float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
return r; return r;
} }
uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, float_status *fpst,
uint32_t ahp_mode)
{ {
/* Squash FZ16 to 0 for the duration of conversion. In this case, /* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing output denormals. * it would affect flushing output denormals.
*/ */
float_status *fpst = fpstp;
bool save = get_flush_to_zero(fpst); bool save = get_flush_to_zero(fpst);
set_flush_to_zero(false, fpst); set_flush_to_zero(false, fpst);
float16 r = float64_to_float16(a, !ahp_mode, fpst); float16 r = float64_to_float16(a, !ahp_mode, fpst);
@ -664,9 +656,8 @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
} }
} }
uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst)
{ {
float_status *fpst = fpstp;
float16 f16 = float16_squash_input_denormal(input, fpst); float16 f16 = float16_squash_input_denormal(input, fpst);
uint32_t f16_val = float16_val(f16); uint32_t f16_val = float16_val(f16);
uint32_t f16_sign = float16_is_neg(f16); uint32_t f16_sign = float16_is_neg(f16);
@ -714,9 +705,8 @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
return make_float16(f16_val); return make_float16(f16_val);
} }
float32 HELPER(recpe_f32)(float32 input, void *fpstp) float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
{ {
float_status *fpst = fpstp;
float32 f32 = float32_squash_input_denormal(input, fpst); float32 f32 = float32_squash_input_denormal(input, fpst);
uint32_t f32_val = float32_val(f32); uint32_t f32_val = float32_val(f32);
bool f32_sign = float32_is_neg(f32); bool f32_sign = float32_is_neg(f32);
@ -764,9 +754,8 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
return make_float32(f32_val); return make_float32(f32_val);
} }
float64 HELPER(recpe_f64)(float64 input, void *fpstp) float64 HELPER(recpe_f64)(float64 input, float_status *fpst)
{ {
float_status *fpst = fpstp;
float64 f64 = float64_squash_input_denormal(input, fpst); float64 f64 = float64_squash_input_denormal(input, fpst);
uint64_t f64_val = float64_val(f64); uint64_t f64_val = float64_val(f64);
bool f64_sign = float64_is_neg(f64); bool f64_sign = float64_is_neg(f64);
@ -865,9 +854,8 @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
return extract64(estimate, 0, 8) << 44; return extract64(estimate, 0, 8) << 44;
} }
uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s)
{ {
float_status *s = fpstp;
float16 f16 = float16_squash_input_denormal(input, s); float16 f16 = float16_squash_input_denormal(input, s);
uint16_t val = float16_val(f16); uint16_t val = float16_val(f16);
bool f16_sign = float16_is_neg(f16); bool f16_sign = float16_is_neg(f16);
@ -880,7 +868,7 @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
if (float16_is_signaling_nan(f16, s)) { if (float16_is_signaling_nan(f16, s)) {
float_raise(float_flag_invalid, s); float_raise(float_flag_invalid, s);
if (!s->default_nan_mode) { if (!s->default_nan_mode) {
nan = float16_silence_nan(f16, fpstp); nan = float16_silence_nan(f16, s);
} }
} }
if (s->default_nan_mode) { if (s->default_nan_mode) {
@ -911,9 +899,8 @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
return make_float16(val); return make_float16(val);
} }
float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
{ {
float_status *s = fpstp;
float32 f32 = float32_squash_input_denormal(input, s); float32 f32 = float32_squash_input_denormal(input, s);
uint32_t val = float32_val(f32); uint32_t val = float32_val(f32);
uint32_t f32_sign = float32_is_neg(f32); uint32_t f32_sign = float32_is_neg(f32);
@ -926,7 +913,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
if (float32_is_signaling_nan(f32, s)) { if (float32_is_signaling_nan(f32, s)) {
float_raise(float_flag_invalid, s); float_raise(float_flag_invalid, s);
if (!s->default_nan_mode) { if (!s->default_nan_mode) {
nan = float32_silence_nan(f32, fpstp); nan = float32_silence_nan(f32, s);
} }
} }
if (s->default_nan_mode) { if (s->default_nan_mode) {
@ -957,9 +944,8 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
return make_float32(val); return make_float32(val);
} }
float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) float64 HELPER(rsqrte_f64)(float64 input, float_status *s)
{ {
float_status *s = fpstp;
float64 f64 = float64_squash_input_denormal(input, s); float64 f64 = float64_squash_input_denormal(input, s);
uint64_t val = float64_val(f64); uint64_t val = float64_val(f64);
bool f64_sign = float64_is_neg(f64); bool f64_sign = float64_is_neg(f64);
@ -971,7 +957,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
if (float64_is_signaling_nan(f64, s)) { if (float64_is_signaling_nan(f64, s)) {
float_raise(float_flag_invalid, s); float_raise(float_flag_invalid, s);
if (!s->default_nan_mode) { if (!s->default_nan_mode) {
nan = float64_silence_nan(f64, fpstp); nan = float64_silence_nan(f64, s);
} }
} }
if (s->default_nan_mode) { if (s->default_nan_mode) {
@ -1026,41 +1012,40 @@ uint32_t HELPER(rsqrte_u32)(uint32_t a)
/* VFPv4 fused multiply-accumulate */ /* VFPv4 fused multiply-accumulate */
dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
dh_ctype_f16 c, void *fpstp) dh_ctype_f16 c, float_status *fpst)
{ {
float_status *fpst = fpstp;
return float16_muladd(a, b, c, 0, fpst); return float16_muladd(a, b, c, 0, fpst);
} }
float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c,
float_status *fpst)
{ {
float_status *fpst = fpstp;
return float32_muladd(a, b, c, 0, fpst); return float32_muladd(a, b, c, 0, fpst);
} }
float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c,
float_status *fpst)
{ {
float_status *fpst = fpstp;
return float64_muladd(a, b, c, 0, fpst); return float64_muladd(a, b, c, 0, fpst);
} }
/* ARMv8 round to integral */ /* ARMv8 round to integral */
dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, float_status *fp_status)
{ {
return float16_round_to_int(x, fp_status); return float16_round_to_int(x, fp_status);
} }
float32 HELPER(rints_exact)(float32 x, void *fp_status) float32 HELPER(rints_exact)(float32 x, float_status *fp_status)
{ {
return float32_round_to_int(x, fp_status); return float32_round_to_int(x, fp_status);
} }
float64 HELPER(rintd_exact)(float64 x, void *fp_status) float64 HELPER(rintd_exact)(float64 x, float_status *fp_status)
{ {
return float64_round_to_int(x, fp_status); return float64_round_to_int(x, fp_status);
} }
dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, float_status *fp_status)
{ {
int old_flags = get_float_exception_flags(fp_status), new_flags; int old_flags = get_float_exception_flags(fp_status), new_flags;
float16 ret; float16 ret;
@ -1076,7 +1061,7 @@ dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
return ret; return ret;
} }
float32 HELPER(rints)(float32 x, void *fp_status) float32 HELPER(rints)(float32 x, float_status *fp_status)
{ {
int old_flags = get_float_exception_flags(fp_status), new_flags; int old_flags = get_float_exception_flags(fp_status), new_flags;
float32 ret; float32 ret;
@ -1092,15 +1077,13 @@ float32 HELPER(rints)(float32 x, void *fp_status)
return ret; return ret;
} }
float64 HELPER(rintd)(float64 x, void *fp_status) float64 HELPER(rintd)(float64 x, float_status *fp_status)
{ {
int old_flags = get_float_exception_flags(fp_status), new_flags; int old_flags = get_float_exception_flags(fp_status), new_flags;
float64 ret; float64 ret;
ret = float64_round_to_int(x, fp_status); ret = float64_round_to_int(x, fp_status);
new_flags = get_float_exception_flags(fp_status);
/* Suppress any inexact exceptions the conversion produced */ /* Suppress any inexact exceptions the conversion produced */
if (!(old_flags & float_flag_inexact)) { if (!(old_flags & float_flag_inexact)) {
new_flags = get_float_exception_flags(fp_status); new_flags = get_float_exception_flags(fp_status);
@ -1124,9 +1107,8 @@ const FloatRoundMode arm_rmode_to_sf_map[] = {
* Implement float64 to int32_t conversion without saturation; * Implement float64 to int32_t conversion without saturation;
* the result is supplied modulo 2^32. * the result is supplied modulo 2^32.
*/ */
uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) uint64_t HELPER(fjcvtzs)(float64 value, float_status *status)
{ {
float_status *status = vstatus;
uint32_t frac, e_old, e_new; uint32_t frac, e_old, e_new;
bool inexact; bool inexact;
@ -1198,12 +1180,12 @@ static float32 frint_s(float32 f, float_status *fpst, int intsize)
return (0x100u + 126u + intsize) << 23; return (0x100u + 126u + intsize) << 23;
} }
float32 HELPER(frint32_s)(float32 f, void *fpst) float32 HELPER(frint32_s)(float32 f, float_status *fpst)
{ {
return frint_s(f, fpst, 32); return frint_s(f, fpst, 32);
} }
float32 HELPER(frint64_s)(float32 f, void *fpst) float32 HELPER(frint64_s)(float32 f, float_status *fpst)
{ {
return frint_s(f, fpst, 64); return frint_s(f, fpst, 64);
} }
@ -1246,12 +1228,12 @@ static float64 frint_d(float64 f, float_status *fpst, int intsize)
return (uint64_t)(0x800 + 1022 + intsize) << 52; return (uint64_t)(0x800 + 1022 + intsize) << 52;
} }
float64 HELPER(frint32_d)(float64 f, void *fpst) float64 HELPER(frint32_d)(float64 f, float_status *fpst)
{ {
return frint_d(f, fpst, 32); return frint_d(f, fpst, 32);
} }
float64 HELPER(frint64_d)(float64 f, void *fpst) float64 HELPER(frint64_d)(float64 f, float_status *fpst)
{ {
return frint_d(f, fpst, 64); return frint_d(f, fpst, 64);
} }

20
tests/functional/test_aarch64_sbsaref.py
View File

@ -24,9 +24,9 @@ def fetch_firmware(test):
Used components: Used components:
- Trusted Firmware v2.11.0 - Trusted Firmware v2.12.0
- Tianocore EDK2 4d4f569924 - Tianocore EDK2 edk2-stable202411
- Tianocore EDK2-platforms 3f08401 - Tianocore EDK2-platforms 4b3530d
""" """
@ -62,13 +62,13 @@ class Aarch64SbsarefMachine(QemuSystemTest):
ASSET_FLASH0 = Asset( ASSET_FLASH0 = Asset(
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/' ('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
'20240619-148232/edk2/SBSA_FLASH0.fd.xz'), '20241122-189881/edk2/SBSA_FLASH0.fd.xz'),
'0c954842a590988f526984de22e21ae0ab9cb351a0c99a8a58e928f0c7359cf7') '76eb89d42eebe324e4395329f47447cda9ac920aabcf99aca85424609c3384a5')
ASSET_FLASH1 = Asset( ASSET_FLASH1 = Asset(
('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/' ('https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/'
'20240619-148232/edk2/SBSA_FLASH1.fd.xz'), '20241122-189881/edk2/SBSA_FLASH1.fd.xz'),
'c6ec39374c4d79bb9e9cdeeb6db44732d90bb4a334cec92002b3f4b9cac4b5ee') 'f850f243bd8dbd49c51e061e0f79f1697546938f454aeb59ab7d93e5f0d412fc')
def test_sbsaref_edk2_firmware(self): def test_sbsaref_edk2_firmware(self):
@ -86,15 +86,15 @@ class Aarch64SbsarefMachine(QemuSystemTest):
# AP Trusted ROM # AP Trusted ROM
wait_for_console_pattern(self, "Booting Trusted Firmware") wait_for_console_pattern(self, "Booting Trusted Firmware")
wait_for_console_pattern(self, "BL1: v2.11.0(release):") wait_for_console_pattern(self, "BL1: v2.12.0(release):")
wait_for_console_pattern(self, "BL1: Booting BL2") wait_for_console_pattern(self, "BL1: Booting BL2")
# Trusted Boot Firmware # Trusted Boot Firmware
wait_for_console_pattern(self, "BL2: v2.11.0(release)") wait_for_console_pattern(self, "BL2: v2.12.0(release)")
wait_for_console_pattern(self, "Booting BL31") wait_for_console_pattern(self, "Booting BL31")
# EL3 Runtime Software # EL3 Runtime Software
wait_for_console_pattern(self, "BL31: v2.11.0(release)") wait_for_console_pattern(self, "BL31: v2.12.0(release)")
# Non-trusted Firmware # Non-trusted Firmware
wait_for_console_pattern(self, "UEFI firmware (version 1.0") wait_for_console_pattern(self, "UEFI firmware (version 1.0")

27
tests/tcg/aarch64/system/feat-xs.c Normal file
View File

@ -0,0 +1,27 @@
/*
* FEAT_XS Test
*
* Copyright (c) 2024 Linaro Ltd
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <minilib.h>
#include <stdint.h>
int main(void)
{
uint64_t isar1;
asm volatile ("mrs %0, id_aa64isar1_el1" : "=r"(isar1));
if (((isar1 >> 56) & 0xf) < 1) {
ml_printf("FEAT_XS not supported by CPU");
return 1;
}
/* VMALLE1NXS */
asm volatile (".inst 0xd508971f");
/* VMALLE1OSNXS */
asm volatile (".inst 0xd508911f");
return 0;
}