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target/riscv: fix access permission checks for CSR_SSP

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Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.2.1. Shadow Stack Pointer
(ssp) CSR access contr" in the priv spec.

Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls
for zicfiss". Thanks to Adam Zabrocki for bringing this to attention.

Reported-by: Adam Zabrocki <azabrocki@nvidia.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250306064636.452396-1-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Deepak Gupta 2025-03-05 22:46:35 -08:00 committed by Alistair Francis
parent 17288e38be
commit 86c78b2806
1 changed files with 5 additions and 0 deletions
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5
target/riscv/csr.c
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@ -192,6 +192,11 @@ static RISCVException cfi_ss(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
} }
/* If ext implemented, M-mode always have access to SSP CSR */
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
/* if bcfi not active for current env, access to csr is illegal */ /* if bcfi not active for current env, access to csr is illegal */
if (!cpu_get_bcfien(env)) { if (!cpu_get_bcfien(env)) {
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)