target/arm: Convert load/store exclusive and ordered to decodetree
Convert the instructions in the load/store exclusive (STXR, STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, LDAR, LDLAR) to decodetree. Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding in the legacy decoder where we were not checking that the RES1 bits in the Rs and Rt2 fields were set. The new function ldst_iss_sf() is equivalent to the existing disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field rather than taking an undecoded two-bit opc field and extracting 'ext' from it. Once all the loads and stores have been converted to decodetree disas_ldst_compute_iss_sf() will be unused and can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
a97d3c18f6
commit
84693e67fa
@ -230,3 +230,14 @@ HLT 1101 0100 010 ................ 000 00 @i16
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# DCPS1 1101 0100 101 ................ 000 01 @i16
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# DCPS1 1101 0100 101 ................ 000 01 @i16
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# DCPS2 1101 0100 101 ................ 000 10 @i16
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# DCPS2 1101 0100 101 ................ 000 10 @i16
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# DCPS3 1101 0100 101 ................ 000 11 @i16
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# DCPS3 1101 0100 101 ................ 000 11 @i16
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# Loads and stores
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&stxr rn rt rt2 rs sz lasr
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&stlr rn rt sz lasr
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@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
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@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr
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STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR
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LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR
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STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR
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LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR
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@ -2652,6 +2652,95 @@ static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
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return regsize == 64;
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return regsize == 64;
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}
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}
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static bool ldst_iss_sf(int size, bool sign, bool ext)
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{
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if (sign) {
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/*
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* Signed loads are 64 bit results if we are not going to
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* do a zero-extend from 32 to 64 after the load.
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* (For a store, sign and ext are always false.)
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*/
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return !ext;
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} else {
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/* Unsigned loads/stores work at the specified size */
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return size == MO_64;
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}
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}
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static bool trans_STXR(DisasContext *s, arg_stxr *a)
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{
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if (a->rn == 31) {
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gen_check_sp_alignment(s);
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}
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if (a->lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false);
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return true;
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}
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static bool trans_LDXR(DisasContext *s, arg_stxr *a)
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{
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if (a->rn == 31) {
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gen_check_sp_alignment(s);
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}
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gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false);
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if (a->lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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return true;
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}
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static bool trans_STLR(DisasContext *s, arg_stlr *a)
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{
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TCGv_i64 clean_addr;
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MemOp memop;
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bool iss_sf = ldst_iss_sf(a->sz, false, false);
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/*
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* StoreLORelease is the same as Store-Release for QEMU, but
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* needs the feature-test.
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*/
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if (!a->lasr && !dc_isar_feature(aa64_lor, s)) {
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return false;
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}
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/* Generate ISS for non-exclusive accesses including LASR. */
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if (a->rn == 31) {
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gen_check_sp_alignment(s);
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}
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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memop = check_ordered_align(s, a->rn, 0, true, a->sz);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn),
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true, a->rn != 31, memop);
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do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt,
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iss_sf, a->lasr);
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return true;
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}
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static bool trans_LDAR(DisasContext *s, arg_stlr *a)
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{
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TCGv_i64 clean_addr;
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MemOp memop;
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bool iss_sf = ldst_iss_sf(a->sz, false, false);
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/* LoadLOAcquire is the same as Load-Acquire for QEMU. */
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if (!a->lasr && !dc_isar_feature(aa64_lor, s)) {
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return false;
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}
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/* Generate ISS for non-exclusive accesses including LASR. */
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if (a->rn == 31) {
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gen_check_sp_alignment(s);
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}
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memop = check_ordered_align(s, a->rn, 0, false, a->sz);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, a->rn),
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false, a->rn != 31, memop);
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do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, memop, false, true,
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a->rt, iss_sf, a->lasr);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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return true;
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}
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/* Load/store exclusive
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/* Load/store exclusive
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*
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*
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* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
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* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
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@ -2674,70 +2763,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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int is_lasr = extract32(insn, 15, 1);
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int is_lasr = extract32(insn, 15, 1);
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int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
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int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
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int size = extract32(insn, 30, 2);
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int size = extract32(insn, 30, 2);
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TCGv_i64 clean_addr;
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MemOp memop;
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switch (o2_L_o1_o0) {
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switch (o2_L_o1_o0) {
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case 0x0: /* STXR */
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case 0x1: /* STLXR */
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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gen_store_exclusive(s, rs, rt, rt2, rn, size, false);
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return;
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case 0x4: /* LDXR */
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case 0x5: /* LDAXR */
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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gen_load_exclusive(s, rt, rt2, rn, size, false);
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if (is_lasr) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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}
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return;
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case 0x8: /* STLLR */
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if (!dc_isar_feature(aa64_lor, s)) {
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break;
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}
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/* StoreLORelease is the same as Store-Release for QEMU. */
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/* fall through */
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case 0x9: /* STLR */
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/* Generate ISS for non-exclusive accesses including LASR. */
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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memop = check_ordered_align(s, rn, 0, true, size);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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true, rn != 31, memop);
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do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt,
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disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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return;
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case 0xc: /* LDLAR */
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if (!dc_isar_feature(aa64_lor, s)) {
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break;
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}
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/* LoadLOAcquire is the same as Load-Acquire for QEMU. */
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/* fall through */
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case 0xd: /* LDAR */
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/* Generate ISS for non-exclusive accesses including LASR. */
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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memop = check_ordered_align(s, rn, 0, false, size);
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clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
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false, rn != 31, memop);
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do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true,
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rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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return;
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case 0x2: case 0x3: /* CASP / STXP */
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case 0x2: case 0x3: /* CASP / STXP */
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if (size & 2) { /* STXP / STLXP */
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if (size & 2) { /* STXP / STLXP */
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if (rn == 31) {
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if (rn == 31) {
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@ -2787,6 +2814,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
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return;
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return;
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}
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}
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break;
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break;
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default:
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/* Handled in decodetree */
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break;
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}
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}
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unallocated_encoding(s);
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unallocated_encoding(s);
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}
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}
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