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target/arm: Pass unpriv bool to get_a64_user_mem_index()

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In every place that we call the get_a64_user_mem_index() function
we do it like this:
 memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
Refactor so the caller passes in the bool that says whether they
want the 'unpriv' or 'normal' mem_index rather than having to
do the ?: themselves.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230912140434.1333369-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-09-12 15:04:25 +01:00
parent dbc678f90a
commit 81466e4bad
1 changed files with 14 additions and 6 deletions
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20
target/arm/tcg/translate-a64.c
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@ -105,9 +105,17 @@ void a64_translate_init(void)
} }
/* /*
* Return the core mmu_idx to use for A64 "unprivileged load/store" insns * Return the core mmu_idx to use for A64 load/store insns which
* have a "unprivileged load/store" variant. Those insns access
* EL0 if executed from an EL which has control over EL0 (usually
* EL1) but behave like normal loads and stores if executed from
* elsewhere (eg EL3).
*
* @unpriv : true for the unprivileged encoding; false for the
* normal encoding (in which case we will return the same
* thing as get_mem_index().
*/ */
static int get_a64_user_mem_index(DisasContext *s) static int get_a64_user_mem_index(DisasContext *s, bool unpriv)
{ {
/* /*
* If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
@ -115,7 +123,7 @@ static int get_a64_user_mem_index(DisasContext *s)
*/ */
ARMMMUIdx useridx = s->mmu_idx; ARMMMUIdx useridx = s->mmu_idx;
if (s->unpriv) { if (unpriv && s->unpriv) {
/* /*
* We have pre-computed the condition for AccType_UNPRIV. * We have pre-computed the condition for AccType_UNPRIV.
* Therefore we should never get here with a mmu_idx for * Therefore we should never get here with a mmu_idx for
@ -3088,7 +3096,7 @@ static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a,
if (!a->p) { if (!a->p) {
tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset);
} }
memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); memidx = get_a64_user_mem_index(s, a->unpriv);
*clean_addr = gen_mte_check1_mmuidx(s, *dirty_addr, is_store, *clean_addr = gen_mte_check1_mmuidx(s, *dirty_addr, is_store,
a->w || a->rn != 31, a->w || a->rn != 31,
mop, a->unpriv, memidx); mop, a->unpriv, memidx);
@ -3109,7 +3117,7 @@ static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a)
{ {
bool iss_sf, iss_valid = !a->w; bool iss_sf, iss_valid = !a->w;
TCGv_i64 clean_addr, dirty_addr, tcg_rt; TCGv_i64 clean_addr, dirty_addr, tcg_rt;
int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); int memidx = get_a64_user_mem_index(s, a->unpriv);
MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN); MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop); op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop);
@ -3127,7 +3135,7 @@ static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a)
{ {
bool iss_sf, iss_valid = !a->w; bool iss_sf, iss_valid = !a->w;
TCGv_i64 clean_addr, dirty_addr, tcg_rt; TCGv_i64 clean_addr, dirty_addr, tcg_rt;
int memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); int memidx = get_a64_user_mem_index(s, a->unpriv);
MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN); MemOp mop = finalize_memop(s, a->sz + a->sign * MO_SIGN);
op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop); op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mop);