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target/sparc: Fix register selection for all F*TOx and FxTO* instructions

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A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.

Cc: qemu-stable@nongnu.org
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder <git@miszr.win>
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
[rth: Squash patches together, since the second fixes a typo in the first.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250205090333.19626-3-git@miszr.win>
This commit is contained in:
Mikael Szreder 2025-02-05 10:03:32 +01:00 committed by Richard Henderson
parent 513823e752
commit 807c3ebd1e
1 changed files with 6 additions and 6 deletions
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12
target/sparc/insns.decode
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@ -321,12 +321,12 @@ FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d
FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r
FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d
FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r
FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @d_r2
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @d_d2
FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2 FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @d_q2
FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_d2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_d2
FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2 FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_d2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2 FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2