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target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE

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WE is the architectural name of the field, not WR.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-29-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:16:59 -07:00
parent 9d63656354
commit 8036281527
3 changed files with 5 additions and 5 deletions
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2
target/nios2/cpu.h
View File

@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_SHIFT 20
#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
#define CR_TLBMISC_RD (1 << 19) #define CR_TLBMISC_RD (1 << 19)
#define CR_TLBMISC_WR (1 << 18) #define CR_TLBMISC_WE (1 << 18)
#define CR_TLBMISC_PID_SHIFT 4 #define CR_TLBMISC_PID_SHIFT 4
#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
#define CR_TLBMISC_DBL (1 << 3) #define CR_TLBMISC_DBL (1 << 3)

4
target/nios2/helper.c
View File

@ -69,7 +69,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
cs->exception_index); cs->exception_index);
env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
env->regs[R_EA] = env->pc + 4; env->regs[R_EA] = env->pc + 4;
env->pc = cpu->fast_tlb_miss_addr; env->pc = cpu->fast_tlb_miss_addr;
@ -104,7 +104,7 @@ void nios2_cpu_do_interrupt(CPUState *cs)
cs->exception_index); cs->exception_index);
if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) { if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) == 0) {
env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WR; env->ctrl[CR_TLBMISC] |= CR_TLBMISC_WE;
} }
env->regs[R_EA] = env->pc + 4; env->regs[R_EA] = env->pc + 4;

4
target/nios2/mmu.c
View File

@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
FIELD_EX32(v, CR_TLBACC, PFN)); FIELD_EX32(v, CR_TLBACC, PFN));
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) {
int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
(v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WR) ? 'W' : '.', (v & CR_TLBMISC_WE) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.',