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tcg/arm: Add full [US]XT[BH] into {s}extract

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The armv6 uxt and sxt opcodes have a 2-bit rotate field
which supports extractions from ofs = {0,8,16,24}.
Special case ofs = 0, len <= 8 as AND.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-25 20:22:45 -08:00
parent 936fc0a96e
commit 802ef65b5f
2 changed files with 67 additions and 8 deletions
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21
tcg/arm/tcg-target-has.h
View File

@ -41,8 +41,8 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions #define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
#define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 1
#define TCG_TARGET_HAS_extract2_i32 1 #define TCG_TARGET_HAS_extract2_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 1
@ -82,4 +82,21 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_HAS_tst_vec 1 #define TCG_TARGET_HAS_tst_vec 1
static inline bool
tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
{
if (use_armv7_instructions) {
return true; /* SBFX or UBFX */
}
switch (len) {
case 8: /* SXTB or UXTB */
case 16: /* SXTH or UXTH */
return (ofs % 8) == 0;
}
return false;
}
#define TCG_TARGET_extract_valid tcg_target_extract_valid
#define TCG_TARGET_sextract_valid tcg_target_extract_valid
#endif #endif

54
tcg/arm/tcg-target.c.inc
View File

@ -1036,19 +1036,61 @@ static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd,
static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd, static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
TCGReg rn, int ofs, int len) TCGReg rn, int ofs, int len)
{ {
/* ubfx */ /* According to gcc, AND can be faster. */
tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn if (ofs == 0 && len <= 8) {
| (ofs << 7) | ((len - 1) << 16)); tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn,
encode_imm_nofail((1 << len) - 1));
return;
}
if (use_armv7_instructions) {
/* ubfx */
tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn
| (ofs << 7) | ((len - 1) << 16));
return;
}
assert(ofs % 8 == 0);
switch (len) {
case 8:
/* uxtb */
tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
break;
case 16:
/* uxth */
tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
break;
default:
g_assert_not_reached();
}
} }
static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd, static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd,
TCGReg rn, int ofs, int len) TCGReg rn, int ofs, int len)
{ {
/* sbfx */ if (use_armv7_instructions) {
tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn /* sbfx */
| (ofs << 7) | ((len - 1) << 16)); tcg_out32(s, 0x07a00050 | (cond << 28) | (rd << 12) | rn
| (ofs << 7) | ((len - 1) << 16));
return;
}
assert(ofs % 8 == 0);
switch (len) {
case 8:
/* sxtb */
tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
break;
case 16:
/* sxth */
tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
break;
default:
g_assert_not_reached();
}
} }
static void tcg_out_ld32u(TCGContext *s, ARMCond cond, static void tcg_out_ld32u(TCGContext *s, ARMCond cond,
TCGReg rd, TCGReg rn, int32_t offset) TCGReg rd, TCGReg rn, int32_t offset)
{ {