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target/riscv/tcg: do not use "!generic" CPU checks

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Our current logic in get/setters of MISA and multi-letter extensions
works because we have only 2 CPU types, generic and vendor, and by using
"!generic" we're implying that we're talking about vendor CPUs. When adding
a third CPU type this logic will break so let's handle it beforehand.

In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu instead
of "not generic". The "generic CPU" checks remaining are from
riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before
applying default values for the extensions.

This leaves us with:

- vendor CPUs will not allow extension enablement, all other CPUs will;

- generic CPUs will inherit default values for extensions, all others
  won't.

And now we can add a new, third CPU type, that will allow extensions to
be enabled and will not inherit defaults, without changing the existing
logic.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-12-18 09:53:10 -03:00 committed by Alistair Francis
parent ee557ad531
commit 7fc3796219
1 changed files with 9 additions and 4 deletions
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13
target/riscv/tcg/tcg-cpu.c
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@ -668,6 +668,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
} }
static bool riscv_cpu_is_vendor(Object *cpu_obj)
{
return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL;
}
/* /*
* We'll get here via the following path: * We'll get here via the following path:
* *
@ -736,7 +741,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
target_ulong misa_bit = misa_ext_cfg->misa_bit; target_ulong misa_bit = misa_ext_cfg->misa_bit;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
bool generic_cpu = riscv_cpu_is_generic(obj); bool vendor_cpu = riscv_cpu_is_vendor(obj);
bool prev_val, value; bool prev_val, value;
if (!visit_type_bool(v, name, &value, errp)) { if (!visit_type_bool(v, name, &value, errp)) {
@ -750,7 +755,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
} }
if (value) { if (value) {
if (!generic_cpu) { if (vendor_cpu) {
g_autofree char *cpuname = riscv_cpu_get_name(cpu); g_autofree char *cpuname = riscv_cpu_get_name(cpu);
error_setg(errp, "'%s' CPU does not allow enabling extensions", error_setg(errp, "'%s' CPU does not allow enabling extensions",
cpuname); cpuname);
@ -855,7 +860,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
{ {
const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
bool generic_cpu = riscv_cpu_is_generic(obj); bool vendor_cpu = riscv_cpu_is_vendor(obj);
bool prev_val, value; bool prev_val, value;
if (!visit_type_bool(v, name, &value, errp)) { if (!visit_type_bool(v, name, &value, errp)) {
@ -879,7 +884,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
return; return;
} }
if (value && !generic_cpu) { if (value && vendor_cpu) {
g_autofree char *cpuname = riscv_cpu_get_name(cpu); g_autofree char *cpuname = riscv_cpu_get_name(cpu);
error_setg(errp, "'%s' CPU does not allow enabling extensions", error_setg(errp, "'%s' CPU does not allow enabling extensions",
cpuname); cpuname);