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target/arm: Convert disas_add_sub_ext_reg to decodetree

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This includes ADD, SUB, ADDS, SUBS (extended register).

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:39 -06:00 committed by Peter Maydell
parent 03a1723bd1
commit 7e16f3c3d4
2 changed files with 29 additions and 45 deletions
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9
target/arm/tcg/a64.decode
View File

@ -727,6 +727,15 @@ ANDS_r . 11 01010 .. . ..... ...... ..... ..... @logic_shift
# Add/subtract (shifted reg)
# Add/subtract (extended reg)
&addsub_ext rd rn rm sf sa st
@addsub_ext sf:1 .. ........ rm:5 st:3 sa:3 rn:5 rd:5 &addsub_ext
ADD_ext . 00 01011001 ..... ... ... ..... ..... @addsub_ext
SUB_ext . 10 01011001 ..... ... ... ..... ..... @addsub_ext
ADDS_ext . 01 01011001 ..... ... ... ..... ..... @addsub_ext
SUBS_ext . 11 01011001 ..... ... ... ..... ..... @addsub_ext
# Add/subtract (carry)
# Rotate right into flags
# Evaluate into flags

65
target/arm/tcg/translate-a64.c
View File

@ -7864,57 +7864,27 @@ TRANS(AND_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, false)
TRANS(ANDS_r, do_logic_reg, a, tcg_gen_and_i64, tcg_gen_andc_i64, true)
TRANS(EOR_r, do_logic_reg, a, tcg_gen_xor_i64, tcg_gen_eqv_i64, false)
/*
* Add/subtract (extended register)
*
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
* |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
*
* sf: 0 -> 32bit, 1 -> 64bit
* op: 0 -> add , 1 -> sub
* S: 1 -> set flags
* opt: 00
* option: extension type (see DecodeRegExtend)
* imm3: optional shift to Rm
*
* Rd = Rn + LSL(extend(Rm), amount)
*/
static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
static bool do_addsub_ext(DisasContext *s, arg_addsub_ext *a,
bool sub_op, bool setflags)
{
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int imm3 = extract32(insn, 10, 3);
int option = extract32(insn, 13, 3);
int rm = extract32(insn, 16, 5);
int opt = extract32(insn, 22, 2);
bool setflags = extract32(insn, 29, 1);
bool sub_op = extract32(insn, 30, 1);
bool sf = extract32(insn, 31, 1);
TCGv_i64 tcg_rm, tcg_rn, tcg_rd, tcg_result;
TCGv_i64 tcg_rm, tcg_rn; /* temps */
TCGv_i64 tcg_rd;
TCGv_i64 tcg_result;
if (imm3 > 4 || opt != 0) {
unallocated_encoding(s);
return;
if (a->sa > 4) {
return false;
}
/* non-flag setting ops may use SP */
if (!setflags) {
tcg_rd = cpu_reg_sp(s, rd);
tcg_rd = cpu_reg_sp(s, a->rd);
} else {
tcg_rd = cpu_reg(s, rd);
tcg_rd = cpu_reg(s, a->rd);
}
tcg_rn = read_cpu_reg_sp(s, rn, sf);
tcg_rn = read_cpu_reg_sp(s, a->rn, a->sf);
tcg_rm = read_cpu_reg(s, rm, sf);
ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
tcg_rm = read_cpu_reg(s, a->rm, a->sf);
ext_and_shift_reg(tcg_rm, tcg_rm, a->st, a->sa);
tcg_result = tcg_temp_new_i64();
if (!setflags) {
if (sub_op) {
tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
@ -7923,19 +7893,25 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
}
} else {
if (sub_op) {
gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
gen_sub_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
} else {
gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
gen_add_CC(a->sf, tcg_result, tcg_rn, tcg_rm);
}
}
if (sf) {
if (a->sf) {
tcg_gen_mov_i64(tcg_rd, tcg_result);
} else {
tcg_gen_ext32u_i64(tcg_rd, tcg_result);
}
return true;
}
TRANS(ADD_ext, do_addsub_ext, a, false, false)
TRANS(SUB_ext, do_addsub_ext, a, true, false)
TRANS(ADDS_ext, do_addsub_ext, a, false, true)
TRANS(SUBS_ext, do_addsub_ext, a, true, true)
/*
* Add/subtract (shifted register)
*
@ -8374,8 +8350,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
if (!op1) {
if (op2 & 8) {
if (op2 & 1) {
/* Add/sub (extended register) */
disas_add_sub_ext_reg(s, insn);
goto do_unallocated;
} else {
/* Add/sub (shifted register) */
disas_add_sub_reg(s, insn);