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fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed

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Our float_flag_output_denormal exception flag is set when
the fpu code flushes an output denormal to zero. Rename
it to float_flag_output_denormal_flushed:
 * this keeps it parallel with the flag for flushing
   input denormals, which we just renamed
 * it makes it clearer that it doesn't mean "set when
   the output is a denormal"

Commit created with
 for f in `git grep -l float_flag_output_denormal`; do sed -i -e 's/float_flag_output_denormal/float_flag_output_denormal_flushed/' $f; done

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250124162836.2332150-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2025-01-24 16:27:40 +00:00
parent 584b7aec81
commit 7af64d103d
9 changed files with 12 additions and 11 deletions
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2
fpu/softfloat-parts.c.inc
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@ -334,7 +334,7 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s,
} }
frac_shr(p, frac_shift); frac_shr(p, frac_shift);
} else if (s->flush_to_zero) { } else if (s->flush_to_zero) {
flags |= float_flag_output_denormal; flags |= float_flag_output_denormal_flushed;
p->cls = float_class_zero; p->cls = float_class_zero;
exp = 0; exp = 0;
frac_clear(p); frac_clear(p);

2
fpu/softfloat.c
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@ -5017,7 +5017,7 @@ floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign,
} }
if ( zExp <= 0 ) { if ( zExp <= 0 ) {
if (status->flush_to_zero) { if (status->flush_to_zero) {
float_raise(float_flag_output_denormal, status); float_raise(float_flag_output_denormal_flushed, status);
return packFloatx80(zSign, 0, 0); return packFloatx80(zSign, 0, 0);
} }
isTiny = status->tininess_before_rounding isTiny = status->tininess_before_rounding

3
include/fpu/softfloat-types.h
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@ -156,7 +156,8 @@ enum {
float_flag_inexact = 0x0010, float_flag_inexact = 0x0010,
/* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */ /* We flushed an input denormal to 0 (because of flush_inputs_to_zero) */
float_flag_input_denormal_flushed = 0x0020, float_flag_input_denormal_flushed = 0x0020,
float_flag_output_denormal = 0x0040, /* We flushed an output denormal to 0 (because of flush_to_zero) */
float_flag_output_denormal_flushed = 0x0040,
float_flag_invalid_isi = 0x0080, /* inf - inf */ float_flag_invalid_isi = 0x0080, /* inf - inf */
float_flag_invalid_imz = 0x0100, /* inf * 0 */ float_flag_invalid_imz = 0x0100, /* inf * 0 */
float_flag_invalid_idi = 0x0200, /* inf / inf */ float_flag_invalid_idi = 0x0200, /* inf / inf */

2
target/arm/vfp_helper.c
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@ -47,7 +47,7 @@ static inline uint32_t vfp_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_overflow) { if (host_bits & float_flag_overflow) {
target_bits |= FPSR_OFC; target_bits |= FPSR_OFC;
} }
if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) {
target_bits |= FPSR_UFC; target_bits |= FPSR_UFC;
} }
if (host_bits & float_flag_inexact) { if (host_bits & float_flag_inexact) {

2
target/i386/tcg/fpu_helper.c
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@ -3268,7 +3268,7 @@ void update_mxcsr_from_sse_status(CPUX86State *env)
(flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) | (flags & float_flag_underflow ? FPUS_UE : 0) |
(flags & float_flag_inexact ? FPUS_PE : 0) | (flags & float_flag_inexact ? FPUS_PE : 0) |
(flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE : (flags & float_flag_output_denormal_flushed ? FPUS_UE | FPUS_PE :
0)); 0));
} }

2
target/m68k/fpu_helper.c
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@ -175,7 +175,7 @@ static int cpu_m68k_exceptbits_from_host(int host_bits)
if (host_bits & float_flag_overflow) { if (host_bits & float_flag_overflow) {
target_bits |= 0x40; target_bits |= 0x40;
} }
if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) {
target_bits |= 0x20; target_bits |= 0x20;
} }
if (host_bits & float_flag_divbyzero) { if (host_bits & float_flag_divbyzero) {

2
target/mips/tcg/msa_helper.c
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@ -6241,7 +6241,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
} }
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */ /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
if ((ieee_exception_flags & float_flag_output_denormal) && if ((ieee_exception_flags & float_flag_output_denormal_flushed) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
mips_exception_flags |= FP_INEXACT; mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) { if (action & CLEAR_FS_UNDERFLOW) {

2
target/rx/op_helper.c
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@ -100,7 +100,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr)
SET_FPSW(X); SET_FPSW(X);
} }
if ((xcpt & (float_flag_input_denormal_flushed if ((xcpt & (float_flag_input_denormal_flushed
| float_flag_output_denormal)) | float_flag_output_denormal_flushed))
&& !FIELD_EX32(env->fpsw, FPSW, DN)) { && !FIELD_EX32(env->fpsw, FPSW, DN)) {
env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1); env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1);
} }

6
target/tricore/fpu_helper.c
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@ -43,7 +43,7 @@ static inline uint8_t f_get_excp_flags(CPUTriCoreState *env)
& (float_flag_invalid & (float_flag_invalid
| float_flag_overflow | float_flag_overflow
| float_flag_underflow | float_flag_underflow
| float_flag_output_denormal | float_flag_output_denormal_flushed
| float_flag_divbyzero | float_flag_divbyzero
| float_flag_inexact); | float_flag_inexact);
} }
@ -99,7 +99,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
some_excp = 1; some_excp = 1;
} }
if (flags & float_flag_underflow || flags & float_flag_output_denormal) { if (flags & float_flag_underflow || flags & float_flag_output_denormal_flushed) {
env->FPU_FU = 1 << 31; env->FPU_FU = 1 << 31;
some_excp = 1; some_excp = 1;
} }
@ -109,7 +109,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
some_excp = 1; some_excp = 1;
} }
if (flags & float_flag_inexact || flags & float_flag_output_denormal) { if (flags & float_flag_inexact || flags & float_flag_output_denormal_flushed) {
env->PSW |= 1 << 26; env->PSW |= 1 << 26;
some_excp = 1; some_excp = 1;
} }