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hw/timer/imx_epit: factor out register write handlers

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Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Axel Heider 2022-10-27 15:09:58 +02:00 committed by Peter Maydell
parent 3d46158125
commit 793a6ea075
1 changed files with 117 additions and 98 deletions
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55
hw/timer/imx_epit.c
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@ -191,20 +191,12 @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
} }
} }
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
unsigned size)
{ {
IMXEPITState *s = IMX_EPIT(opaque); uint32_t oldcr = s->cr;
uint64_t oldcr;
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
(uint32_t)value);
switch (offset >> 2) {
case 0: /* CR */
oldcr = s->cr;
s->cr = value & 0x03ffffff; s->cr = value & 0x03ffffff;
if (s->cr & CR_SWR) { if (s->cr & CR_SWR) {
/* handle the reset */ /* handle the reset */
imx_epit_reset(s, false); imx_epit_reset(s, false);
@ -263,17 +255,19 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_cmp);
ptimer_transaction_commit(s->timer_reload); ptimer_transaction_commit(s->timer_reload);
break; }
case 1: /* SR - ACK*/ static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
{
/* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
if (value & SR_OCIF) { if (value & SR_OCIF) {
s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
imx_epit_update_int(s); imx_epit_update_int(s);
} }
break; }
case 2: /* LR - set ticks */ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
{
s->lr = value; s->lr = value;
ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_cmp);
@ -296,24 +290,49 @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
ptimer_transaction_commit(s->timer_reload); ptimer_transaction_commit(s->timer_reload);
imx_epit_reload_compare_timer(s); imx_epit_reload_compare_timer(s);
ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_cmp);
break; }
case 3: /* CMP */ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
{
s->cmp = value; s->cmp = value;
ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_cmp);
imx_epit_reload_compare_timer(s); imx_epit_reload_compare_timer(s);
ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_cmp);
}
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
IMXEPITState *s = IMX_EPIT(opaque);
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
(uint32_t)value);
switch (offset >> 2) {
case 0: /* CR */
imx_epit_write_cr(s, (uint32_t)value);
break;
case 1: /* SR */
imx_epit_write_sr(s, (uint32_t)value);
break;
case 2: /* LR */
imx_epit_write_lr(s, (uint32_t)value);
break;
case 3: /* CMP */
imx_epit_write_cmp(s, (uint32_t)value);
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
break; break;
} }
} }
static void imx_epit_cmp(void *opaque) static void imx_epit_cmp(void *opaque)
{ {
IMXEPITState *s = IMX_EPIT(opaque); IMXEPITState *s = IMX_EPIT(opaque);