tcg: Drop implementation checks from tcg-opc.h
Now that we use a functional interface to query whether the opcode is supported, we can drop the TCG_OPF_NOT_PRESENT bit mapping from TCG_TARGET_HAS_foo in tcg-opc.h Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
931bac71fc
commit
76187b4f57
@ -35,18 +35,11 @@ DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
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DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
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DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
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#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
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#if TCG_TARGET_REG_BITS == 32
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# define IMPL64 TCG_OPF_NOT_PRESENT
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#else
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# define IMPL64 0
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#endif
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DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
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DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
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DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(setcond_i32, 1, 2, 1, 0)
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DEF(setcond_i32, 1, 2, 1, 0)
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DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond_i32))
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DEF(negsetcond_i32, 1, 2, 1, 0)
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DEF(movcond_i32, 1, 4, 1, 0)
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DEF(movcond_i32, 1, 4, 1, 0)
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/* load/store */
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/* load/store */
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DEF(ld8u_i32, 1, 1, 1, 0)
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DEF(ld8u_i32, 1, 1, 1, 0)
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@ -61,12 +54,12 @@ DEF(st_i32, 0, 2, 1, 0)
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DEF(add_i32, 1, 2, 0, 0)
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DEF(add_i32, 1, 2, 0, 0)
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DEF(sub_i32, 1, 2, 0, 0)
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DEF(sub_i32, 1, 2, 0, 0)
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DEF(mul_i32, 1, 2, 0, 0)
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DEF(mul_i32, 1, 2, 0, 0)
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DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(div_i32, 1, 2, 0, 0)
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DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
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DEF(divu_i32, 1, 2, 0, 0)
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DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
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DEF(rem_i32, 1, 2, 0, 0)
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DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
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DEF(remu_i32, 1, 2, 0, 0)
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DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(div2_i32, 2, 3, 0, 0)
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DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
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DEF(divu2_i32, 2, 3, 0, 0)
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DEF(and_i32, 1, 2, 0, 0)
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DEF(and_i32, 1, 2, 0, 0)
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DEF(or_i32, 1, 2, 0, 0)
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DEF(or_i32, 1, 2, 0, 0)
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DEF(xor_i32, 1, 2, 0, 0)
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DEF(xor_i32, 1, 2, 0, 0)
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@ -74,119 +67,114 @@ DEF(xor_i32, 1, 2, 0, 0)
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DEF(shl_i32, 1, 2, 0, 0)
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DEF(shl_i32, 1, 2, 0, 0)
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(rotl_i32, 1, 2, 0, 0)
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DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
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DEF(rotr_i32, 1, 2, 0, 0)
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DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
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DEF(deposit_i32, 1, 2, 2, 0)
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DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
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DEF(extract_i32, 1, 1, 2, 0)
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DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
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DEF(sextract_i32, 1, 1, 2, 0)
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DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
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DEF(extract2_i32, 1, 2, 1, 0)
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
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DEF(add2_i32, 2, 4, 0, 0)
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DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
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DEF(sub2_i32, 2, 4, 0, 0)
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DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
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DEF(mulu2_i32, 2, 2, 0, 0)
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DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
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DEF(muls2_i32, 2, 2, 0, 0)
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DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
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DEF(muluh_i32, 1, 2, 0, 0)
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DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
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DEF(mulsh_i32, 1, 2, 0, 0)
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DEF(brcond2_i32, 0, 4, 2,
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DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(setcond2_i32, 1, 4, 1, 0)
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DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
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DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
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DEF(ext8s_i32, 1, 1, 0, 0)
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DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
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DEF(ext16s_i32, 1, 1, 0, 0)
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DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
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DEF(ext8u_i32, 1, 1, 0, 0)
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DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
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DEF(ext16u_i32, 1, 1, 0, 0)
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DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32))
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DEF(bswap16_i32, 1, 1, 1, 0)
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DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32))
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DEF(bswap32_i32, 1, 1, 1, 0)
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DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
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DEF(not_i32, 1, 1, 0, 0)
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DEF(neg_i32, 1, 1, 0, 0)
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DEF(neg_i32, 1, 1, 0, 0)
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DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
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DEF(andc_i32, 1, 2, 0, 0)
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DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
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DEF(orc_i32, 1, 2, 0, 0)
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DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
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DEF(eqv_i32, 1, 2, 0, 0)
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DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
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DEF(nand_i32, 1, 2, 0, 0)
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DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
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DEF(nor_i32, 1, 2, 0, 0)
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DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
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DEF(clz_i32, 1, 2, 0, 0)
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DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
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DEF(ctz_i32, 1, 2, 0, 0)
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DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
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DEF(ctpop_i32, 1, 1, 0, 0)
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DEF(mov_i64, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(mov_i64, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(setcond_i64, 1, 2, 1, IMPL64)
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DEF(setcond_i64, 1, 2, 1, 0)
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DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64))
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DEF(negsetcond_i64, 1, 2, 1, 0)
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DEF(movcond_i64, 1, 4, 1, IMPL64)
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DEF(movcond_i64, 1, 4, 1, 0)
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/* load/store */
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/* load/store */
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DEF(ld8u_i64, 1, 1, 1, IMPL64)
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DEF(ld8u_i64, 1, 1, 1, 0)
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DEF(ld8s_i64, 1, 1, 1, IMPL64)
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DEF(ld8s_i64, 1, 1, 1, 0)
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DEF(ld16u_i64, 1, 1, 1, IMPL64)
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DEF(ld16u_i64, 1, 1, 1, 0)
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DEF(ld16s_i64, 1, 1, 1, IMPL64)
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DEF(ld16s_i64, 1, 1, 1, 0)
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DEF(ld32u_i64, 1, 1, 1, IMPL64)
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DEF(ld32u_i64, 1, 1, 1, 0)
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DEF(ld32s_i64, 1, 1, 1, IMPL64)
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DEF(ld32s_i64, 1, 1, 1, 0)
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DEF(ld_i64, 1, 1, 1, IMPL64)
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DEF(ld_i64, 1, 1, 1, 0)
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DEF(st8_i64, 0, 2, 1, IMPL64)
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DEF(st8_i64, 0, 2, 1, 0)
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DEF(st16_i64, 0, 2, 1, IMPL64)
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DEF(st16_i64, 0, 2, 1, 0)
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DEF(st32_i64, 0, 2, 1, IMPL64)
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DEF(st32_i64, 0, 2, 1, 0)
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DEF(st_i64, 0, 2, 1, IMPL64)
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DEF(st_i64, 0, 2, 1, 0)
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/* arith */
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/* arith */
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DEF(add_i64, 1, 2, 0, IMPL64)
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DEF(add_i64, 1, 2, 0, 0)
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DEF(sub_i64, 1, 2, 0, IMPL64)
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DEF(sub_i64, 1, 2, 0, 0)
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DEF(mul_i64, 1, 2, 0, IMPL64)
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DEF(mul_i64, 1, 2, 0, 0)
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DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(div_i64, 1, 2, 0, 0)
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DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
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DEF(divu_i64, 1, 2, 0, 0)
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DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
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DEF(rem_i64, 1, 2, 0, 0)
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DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
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DEF(remu_i64, 1, 2, 0, 0)
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DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(div2_i64, 2, 3, 0, 0)
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DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
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DEF(divu2_i64, 2, 3, 0, 0)
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DEF(and_i64, 1, 2, 0, IMPL64)
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DEF(and_i64, 1, 2, 0, 0)
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DEF(or_i64, 1, 2, 0, IMPL64)
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DEF(or_i64, 1, 2, 0, 0)
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DEF(xor_i64, 1, 2, 0, IMPL64)
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DEF(xor_i64, 1, 2, 0, 0)
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/* shifts/rotates */
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/* shifts/rotates */
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DEF(shl_i64, 1, 2, 0, IMPL64)
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DEF(shl_i64, 1, 2, 0, 0)
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DEF(shr_i64, 1, 2, 0, IMPL64)
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DEF(shr_i64, 1, 2, 0, 0)
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DEF(sar_i64, 1, 2, 0, IMPL64)
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DEF(sar_i64, 1, 2, 0, 0)
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DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(rotl_i64, 1, 2, 0, 0)
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DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
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DEF(rotr_i64, 1, 2, 0, 0)
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DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
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DEF(deposit_i64, 1, 2, 2, 0)
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DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
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DEF(extract_i64, 1, 1, 2, 0)
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DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
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DEF(sextract_i64, 1, 1, 2, 0)
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DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
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DEF(extract2_i64, 1, 2, 1, 0)
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/* size changing ops */
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/* size changing ops */
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DEF(ext_i32_i64, 1, 1, 0, IMPL64)
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DEF(ext_i32_i64, 1, 1, 0, 0)
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DEF(extu_i32_i64, 1, 1, 0, IMPL64)
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DEF(extu_i32_i64, 1, 1, 0, 0)
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DEF(extrl_i64_i32, 1, 1, 0,
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DEF(extrl_i64_i32, 1, 1, 0, 0)
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IMPL(TCG_TARGET_HAS_extr_i64_i32)
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DEF(extrh_i64_i32, 1, 1, 0, 0)
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DEF(extrh_i64_i32, 1, 1, 0,
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IMPL(TCG_TARGET_HAS_extr_i64_i32)
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
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DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
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DEF(ext8s_i64, 1, 1, 0, 0)
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DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
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DEF(ext16s_i64, 1, 1, 0, 0)
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DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
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DEF(ext32s_i64, 1, 1, 0, 0)
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DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
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DEF(ext8u_i64, 1, 1, 0, 0)
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DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
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DEF(ext16u_i64, 1, 1, 0, 0)
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DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
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DEF(ext32u_i64, 1, 1, 0, 0)
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DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
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DEF(bswap16_i64, 1, 1, 1, 0)
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DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
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DEF(bswap32_i64, 1, 1, 1, 0)
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DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
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DEF(bswap64_i64, 1, 1, 1, 0)
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DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
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DEF(not_i64, 1, 1, 0, 0)
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DEF(neg_i64, 1, 1, 0, IMPL64)
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DEF(neg_i64, 1, 1, 0, 0)
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DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
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DEF(andc_i64, 1, 2, 0, 0)
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DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
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DEF(orc_i64, 1, 2, 0, 0)
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DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
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DEF(eqv_i64, 1, 2, 0, 0)
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DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
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DEF(nand_i64, 1, 2, 0, 0)
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DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
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DEF(nor_i64, 1, 2, 0, 0)
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DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
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DEF(clz_i64, 1, 2, 0, 0)
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DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
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DEF(ctz_i64, 1, 2, 0, 0)
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DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
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DEF(ctpop_i64, 1, 1, 0, 0)
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DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
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DEF(add2_i64, 2, 4, 0, 0)
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DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
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DEF(sub2_i64, 2, 4, 0, 0)
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DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
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DEF(mulu2_i64, 2, 2, 0, 0)
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DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
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DEF(muls2_i64, 2, 2, 0, 0)
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DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
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DEF(muluh_i64, 1, 2, 0, 0)
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DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
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DEF(mulsh_i64, 1, 2, 0, 0)
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#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
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#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
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@ -221,34 +209,24 @@ DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1,
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/* Only used by i386 to cope with stupid register constraints. */
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/* Only used by i386 to cope with stupid register constraints. */
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DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
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DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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IMPL(TCG_TARGET_HAS_qemu_st8_i32))
|
|
||||||
DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
|
DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
|
||||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
|
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||||
IMPL(TCG_TARGET_HAS_qemu_st8_i32))
|
|
||||||
|
|
||||||
/* Only for 64-bit hosts at the moment. */
|
/* Only for 64-bit hosts at the moment. */
|
||||||
DEF(qemu_ld_a32_i128, 2, 1, 1,
|
DEF(qemu_ld_a32_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
|
DEF(qemu_ld_a64_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||||
IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
|
DEF(qemu_st_a32_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||||
DEF(qemu_ld_a64_i128, 2, 1, 1,
|
DEF(qemu_st_a64_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
|
|
||||||
IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
|
|
||||||
DEF(qemu_st_a32_i128, 0, 3, 1,
|
|
||||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
|
|
||||||
IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
|
|
||||||
DEF(qemu_st_a64_i128, 0, 3, 1,
|
|
||||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
|
|
||||||
IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
|
|
||||||
|
|
||||||
/* Host vector support. */
|
/* Host vector support. */
|
||||||
|
|
||||||
#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
|
#define IMPLVEC TCG_OPF_VECTOR
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||||||
|
|
||||||
DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
|
DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
|
||||||
|
|
||||||
DEF(dup_vec, 1, 1, 0, IMPLVEC)
|
DEF(dup_vec, 1, 1, 0, IMPLVEC)
|
||||||
DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
|
DEF(dup2_vec, 1, 2, 0, IMPLVEC)
|
||||||
|
|
||||||
DEF(ld_vec, 1, 1, 1, IMPLVEC)
|
DEF(ld_vec, 1, 1, 1, IMPLVEC)
|
||||||
DEF(st_vec, 0, 2, 1, IMPLVEC)
|
DEF(st_vec, 0, 2, 1, IMPLVEC)
|
||||||
@ -256,55 +234,53 @@ DEF(dupm_vec, 1, 1, 1, IMPLVEC)
|
|||||||
|
|
||||||
DEF(add_vec, 1, 2, 0, IMPLVEC)
|
DEF(add_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(sub_vec, 1, 2, 0, IMPLVEC)
|
DEF(sub_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
|
DEF(mul_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
|
DEF(neg_vec, 1, 1, 0, IMPLVEC)
|
||||||
DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
|
DEF(abs_vec, 1, 1, 0, IMPLVEC)
|
||||||
DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
DEF(ssadd_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
DEF(usadd_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
DEF(sssub_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
|
DEF(ussub_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
DEF(smin_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
DEF(umin_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
DEF(smax_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec))
|
DEF(umax_vec, 1, 2, 0, IMPLVEC)
|
||||||
|
|
||||||
DEF(and_vec, 1, 2, 0, IMPLVEC)
|
DEF(and_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(or_vec, 1, 2, 0, IMPLVEC)
|
DEF(or_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(xor_vec, 1, 2, 0, IMPLVEC)
|
DEF(xor_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
|
DEF(andc_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
|
DEF(orc_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec))
|
DEF(nand_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec))
|
DEF(nor_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec))
|
DEF(eqv_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
|
DEF(not_vec, 1, 1, 0, IMPLVEC)
|
||||||
|
|
||||||
DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
DEF(shli_vec, 1, 1, 1, IMPLVEC)
|
||||||
DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
DEF(shri_vec, 1, 1, 1, IMPLVEC)
|
||||||
DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
DEF(sari_vec, 1, 1, 1, IMPLVEC)
|
||||||
DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec))
|
DEF(rotli_vec, 1, 1, 1, IMPLVEC)
|
||||||
|
|
||||||
DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
DEF(shls_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
DEF(shrs_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
DEF(sars_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec))
|
DEF(rotls_vec, 1, 2, 0, IMPLVEC)
|
||||||
|
|
||||||
DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
DEF(shlv_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
DEF(shrv_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
DEF(sarv_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
|
DEF(rotlv_vec, 1, 2, 0, IMPLVEC)
|
||||||
DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec))
|
DEF(rotrv_vec, 1, 2, 0, IMPLVEC)
|
||||||
|
|
||||||
DEF(cmp_vec, 1, 2, 1, IMPLVEC)
|
DEF(cmp_vec, 1, 2, 1, IMPLVEC)
|
||||||
|
|
||||||
DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
|
DEF(bitsel_vec, 1, 3, 0, IMPLVEC)
|
||||||
DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
|
DEF(cmpsel_vec, 1, 4, 1, IMPLVEC)
|
||||||
|
|
||||||
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
|
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
|
||||||
|
|
||||||
#include "tcg-target-opc.h.inc"
|
#include "tcg-target-opc.h.inc"
|
||||||
|
|
||||||
#undef DATA64_ARGS
|
#undef DATA64_ARGS
|
||||||
#undef IMPL
|
|
||||||
#undef IMPL64
|
|
||||||
#undef IMPLVEC
|
#undef IMPLVEC
|
||||||
#undef DEF
|
#undef DEF
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user