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target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:08 -06:00 committed by Peter Maydell
parent 95288cc165
commit 72040d9200
2 changed files with 40 additions and 64 deletions
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10
target/arm/tcg/a64.decode
View File

@ -1635,6 +1635,11 @@ SQABS_s 0101 1110 ..1 00000 01111 0 ..... ..... @rr_e
SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e SQNEG_s 0111 1110 ..1 00000 01111 0 ..... ..... @rr_e
ABS_s 0101 1110 111 00000 10111 0 ..... ..... @rr ABS_s 0101 1110 111 00000 10111 0 ..... ..... @rr
NEG_s 0111 1110 111 00000 10111 0 ..... ..... @rr NEG_s 0111 1110 111 00000 10111 0 ..... ..... @rr
CMGT0_s 0101 1110 111 00000 10001 0 ..... ..... @rr
CMGE0_s 0111 1110 111 00000 10001 0 ..... ..... @rr
CMEQ0_s 0101 1110 111 00000 10011 0 ..... ..... @rr
CMLE0_s 0111 1110 111 00000 10011 0 ..... ..... @rr
CMLT0_s 0101 1110 111 00000 10101 0 ..... ..... @rr
# Advanced SIMD two-register miscellaneous # Advanced SIMD two-register miscellaneous
@ -1647,3 +1652,8 @@ CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e
CNT_v 0.00 1110 001 00000 01011 0 ..... ..... @qrr_b CNT_v 0.00 1110 001 00000 01011 0 ..... ..... @qrr_b
NOT_v 0.10 1110 001 00000 01011 0 ..... ..... @qrr_b NOT_v 0.10 1110 001 00000 01011 0 ..... ..... @qrr_b
RBIT_v 0.10 1110 011 00000 01011 0 ..... ..... @qrr_b RBIT_v 0.10 1110 011 00000 01011 0 ..... ..... @qrr_b
CMGT0_v 0.00 1110 ..1 00000 10001 0 ..... ..... @qrr_e
CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e

94
target/arm/tcg/translate-a64.c
View File

@ -8902,6 +8902,22 @@ static bool do_scalar1_d(DisasContext *s, arg_rr *a, ArithOneOp *f)
TRANS(ABS_s, do_scalar1_d, a, tcg_gen_abs_i64) TRANS(ABS_s, do_scalar1_d, a, tcg_gen_abs_i64)
TRANS(NEG_s, do_scalar1_d, a, tcg_gen_neg_i64) TRANS(NEG_s, do_scalar1_d, a, tcg_gen_neg_i64)
static bool do_cmop0_d(DisasContext *s, arg_rr *a, TCGCond cond)
{
if (fp_access_check(s)) {
TCGv_i64 t = read_fp_dreg(s, a->rn);
tcg_gen_negsetcond_i64(cond, t, t, tcg_constant_i64(0));
write_fp_dreg(s, a->rd, t);
}
return true;
}
TRANS(CMGT0_s, do_cmop0_d, a, TCG_COND_GT)
TRANS(CMGE0_s, do_cmop0_d, a, TCG_COND_GE)
TRANS(CMLE0_s, do_cmop0_d, a, TCG_COND_LE)
TRANS(CMLT0_s, do_cmop0_d, a, TCG_COND_LT)
TRANS(CMEQ0_s, do_cmop0_d, a, TCG_COND_EQ)
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn) static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{ {
if (!a->q && a->esz == MO_64) { if (!a->q && a->esz == MO_64) {
@ -8918,6 +8934,11 @@ TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
TRANS(NOT_v, do_gvec_fn2, a, tcg_gen_gvec_not) TRANS(NOT_v, do_gvec_fn2, a, tcg_gen_gvec_not)
TRANS(CNT_v, do_gvec_fn2, a, gen_gvec_cnt) TRANS(CNT_v, do_gvec_fn2, a, gen_gvec_cnt)
TRANS(RBIT_v, do_gvec_fn2, a, gen_gvec_rbit) TRANS(RBIT_v, do_gvec_fn2, a, gen_gvec_rbit)
TRANS(CMGT0_v, do_gvec_fn2, a, gen_gvec_cgt0)
TRANS(CMGE0_v, do_gvec_fn2, a, gen_gvec_cge0)
TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn) static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{ {
@ -9229,21 +9250,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* The caller only need provide tcg_rmode and tcg_fpstatus if the op * The caller only need provide tcg_rmode and tcg_fpstatus if the op
* requires them. * requires them.
*/ */
TCGCond cond;
switch (opcode) { switch (opcode) {
case 0xa: /* CMLT */
cond = TCG_COND_LT;
do_cmop:
/* 64 bit integer comparison against zero, result is test ? -1 : 0. */
tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_constant_i64(0));
break;
case 0x8: /* CMGT, CMGE */
cond = u ? TCG_COND_GE : TCG_COND_GT;
goto do_cmop;
case 0x9: /* CMEQ, CMLE */
cond = u ? TCG_COND_LE : TCG_COND_EQ;
goto do_cmop;
case 0x2f: /* FABS */ case 0x2f: /* FABS */
gen_vfp_absd(tcg_rd, tcg_rn); gen_vfp_absd(tcg_rd, tcg_rn);
break; break;
@ -9290,6 +9297,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x4: /* CLS, CLZ */ case 0x4: /* CLS, CLZ */
case 0x5: /* NOT */ case 0x5: /* NOT */
case 0x7: /* SQABS, SQNEG */ case 0x7: /* SQABS, SQNEG */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */ case 0xb: /* ABS, NEG */
g_assert_not_reached(); g_assert_not_reached();
} }
@ -9633,19 +9643,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus; TCGv_ptr tcg_fpstatus;
switch (opcode) { switch (opcode) {
case 0xa: /* CMLT */
if (u) {
unallocated_encoding(s);
return;
}
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
if (size != 3) {
unallocated_encoding(s);
return;
}
break;
case 0x12: /* SQXTUN */ case 0x12: /* SQXTUN */
if (!u) { if (!u) {
unallocated_encoding(s); unallocated_encoding(s);
@ -9731,6 +9728,9 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
default: default:
case 0x3: /* USQADD / SUQADD */ case 0x3: /* USQADD / SUQADD */
case 0x7: /* SQABS / SQNEG */ case 0x7: /* SQABS / SQNEG */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */ case 0xb: /* ABS, NEG */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
@ -10103,19 +10103,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} }
handle_shll(s, is_q, size, rn, rd); handle_shll(s, is_q, size, rn, rd);
return; return;
case 0xa: /* CMLT */
if (u == 1) {
unallocated_encoding(s);
return;
}
/* fall through */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0xc ... 0xf: case 0xc ... 0xf:
case 0x16 ... 0x1f: case 0x16 ... 0x1f:
{ {
@ -10289,6 +10276,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x4: /* CLS, CLZ */ case 0x4: /* CLS, CLZ */
case 0x5: /* CNT, NOT, RBIT */ case 0x5: /* CNT, NOT, RBIT */
case 0x7: /* SQABS, SQNEG */ case 0x7: /* SQABS, SQNEG */
case 0x8: /* CMGT, CMGE */
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */ case 0xb: /* ABS, NEG */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
@ -10309,30 +10299,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_rmode = NULL; tcg_rmode = NULL;
} }
switch (opcode) {
case 0x8: /* CMGT, CMGE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cge0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cgt0, size);
}
return;
case 0x9: /* CMEQ, CMLE */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cle0, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_ceq0, size);
}
return;
case 0xa: /* CMLT */
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return;
case 0x4: /* CLZ, CLS */
case 0x5: /* CNT, NOT, RBIT */
case 0xb:
g_assert_not_reached();
}
if (size == 3) { if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */ /* All 64-bit element operations can be shared with scalar 2misc */
int pass; int pass;