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hw/intc/arm_gicv3: Add cast to match the documentation

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The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit.
When cast to uint64_t (for further bitwise OR), the 32 most
significant bits will be filled with 1s. However, the documentation
states that the upper 32 bits of ICC_AP[0/1]R<n>_EL2 are reserved.

Add an explicit cast to match the documentation.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Cc: qemu-stable@nongnu.org
Fixes: 28cca59c46 ("hw/intc/arm_gicv3: Add NMI handling CPU interface registers")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 12dc8f6eca1ead876142fd3d6731cf3da1295f2a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Alexandra Diupina 2024-10-14 17:05:50 +01:00 committed by Michael Tokarev
parent c5f652a053
commit 6fecfc5978
1 changed files with 1 additions and 1 deletions
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hw/intc/arm_gicv3_cpuif.c
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@ -1170,7 +1170,7 @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
if (nmi) { if (nmi) {
cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI; cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI;
} else { } else {
cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit); cs->icc_apr[cs->hppi.grp][regno] |= (1U << regbit);
} }
if (irq < GIC_INTERNAL) { if (irq < GIC_INTERNAL) {