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qemu-sparc queue

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20201028' into staging

qemu-sparc queue

# gpg: Signature made Wed 28 Oct 2020 08:17:23 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-20201028:
  hw/pci-host/sabre: Simplify code initializing variable once
  hw/pci-host/sabre: Remove superfluous address range check
  hw/pci-host/sabre: Update documentation link
  sabre: increase number of PCI bus IRQs from 32 to 64
  hw/display/tcx: Allow 64-bit accesses to framebuffer stippler and blitter
  sabre: don't call sysbus_mmio_map() in sabre_realize()
  sparc32-ledma: don't reference nd_table directly within the device
  sparc32-espdma: use object_initialize_child() for esp child object
  sparc32-ledma: use object_initialize_child() for lance child object
  sparc32-dma: use object_initialize_child() for espdma and ledma child objects

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-10-31 09:48:20 +00:00
commit 69d7eab0b8
6 changed files with 67 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
hw/display/tcx.c
View File

@ -549,20 +549,28 @@ static const MemoryRegionOps tcx_stip_ops = {
.read = tcx_stip_readl, .read = tcx_stip_readl,
.write = tcx_stip_writel, .write = tcx_stip_writel,
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
.valid = { .impl = {
.min_access_size = 4, .min_access_size = 4,
.max_access_size = 4, .max_access_size = 4,
}, },
.valid = {
.min_access_size = 4,
.max_access_size = 8,
},
}; };
static const MemoryRegionOps tcx_rstip_ops = { static const MemoryRegionOps tcx_rstip_ops = {
.read = tcx_stip_readl, .read = tcx_stip_readl,
.write = tcx_rstip_writel, .write = tcx_rstip_writel,
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
.valid = { .impl = {
.min_access_size = 4, .min_access_size = 4,
.max_access_size = 4, .max_access_size = 4,
}, },
.valid = {
.min_access_size = 4,
.max_access_size = 8,
},
}; };
static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, static uint64_t tcx_blit_readl(void *opaque, hwaddr addr,
@ -651,10 +659,14 @@ static const MemoryRegionOps tcx_rblit_ops = {
.read = tcx_blit_readl, .read = tcx_blit_readl,
.write = tcx_rblit_writel, .write = tcx_rblit_writel,
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
.valid = { .impl = {
.min_access_size = 4, .min_access_size = 4,
.max_access_size = 4, .max_access_size = 4,
}, },
.valid = {
.min_access_size = 4,
.max_access_size = 8,
},
}; };
static void tcx_invalidate_cursor_position(TCXState *s) static void tcx_invalidate_cursor_position(TCXState *s)

47
hw/dma/sparc32_dma.c
View File

@ -290,27 +290,26 @@ static const TypeInfo sparc32_dma_device_info = {
static void sparc32_espdma_device_init(Object *obj) static void sparc32_espdma_device_init(Object *obj)
{ {
DMADeviceState *s = SPARC32_DMA_DEVICE(obj); DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"espdma-mmio", DMA_SIZE); "espdma-mmio", DMA_SIZE);
object_initialize_child(obj, "esp", &es->esp, TYPE_ESP);
} }
static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp) static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)
{ {
DeviceState *d; ESPDMADeviceState *es = SPARC32_ESPDMA_DEVICE(dev);
SysBusESPState *sysbus; SysBusESPState *sysbus = ESP(&es->esp);
ESPState *esp; ESPState *esp = &sysbus->esp;
d = qdev_new(TYPE_ESP);
object_property_add_child(OBJECT(dev), "esp", OBJECT(d));
sysbus = ESP(d);
esp = &sysbus->esp;
esp->dma_memory_read = espdma_memory_read; esp->dma_memory_read = espdma_memory_read;
esp->dma_memory_write = espdma_memory_write; esp->dma_memory_write = espdma_memory_write;
esp->dma_opaque = SPARC32_DMA_DEVICE(dev); esp->dma_opaque = SPARC32_DMA_DEVICE(dev);
sysbus->it_shift = 2; sysbus->it_shift = 2;
esp->dma_enabled = 1; esp->dma_enabled = 1;
sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(sysbus), &error_fatal);
} }
static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data) static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)
@ -331,24 +330,21 @@ static const TypeInfo sparc32_espdma_device_info = {
static void sparc32_ledma_device_init(Object *obj) static void sparc32_ledma_device_init(Object *obj)
{ {
DMADeviceState *s = SPARC32_DMA_DEVICE(obj); DMADeviceState *s = SPARC32_DMA_DEVICE(obj);
LEDMADeviceState *ls = SPARC32_LEDMA_DEVICE(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s, memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"ledma-mmio", DMA_SIZE); "ledma-mmio", DMA_SIZE);
object_initialize_child(obj, "lance", &ls->lance, TYPE_LANCE);
} }
static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp) static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)
{ {
DeviceState *d; LEDMADeviceState *s = SPARC32_LEDMA_DEVICE(dev);
NICInfo *nd = &nd_table[0]; SysBusPCNetState *lance = SYSBUS_PCNET(&s->lance);
/* FIXME use qdev NIC properties instead of nd_table[] */ object_property_set_link(OBJECT(lance), "dma", OBJECT(dev), &error_abort);
qemu_check_nic_model(nd, TYPE_LANCE); sysbus_realize(SYS_BUS_DEVICE(lance), &error_fatal);
d = qdev_new(TYPE_LANCE);
object_property_add_child(OBJECT(dev), "lance", OBJECT(d));
qdev_set_nic_properties(d, nd);
object_property_set_link(OBJECT(d), "dma", OBJECT(dev), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(d), &error_fatal);
} }
static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data) static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)
@ -379,10 +375,9 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
return; return;
} }
espdma = qdev_new(TYPE_SPARC32_ESPDMA_DEVICE); espdma = DEVICE(&s->espdma);
object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort); object_property_set_link(OBJECT(espdma), "iommu", iommu, &error_abort);
object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma)); sysbus_realize(SYS_BUS_DEVICE(espdma), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(espdma), &error_fatal);
esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));
sbd = SYS_BUS_DEVICE(esp); sbd = SYS_BUS_DEVICE(esp);
@ -394,10 +389,9 @@ static void sparc32_dma_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->dmamem, 0x0, memory_region_add_subregion(&s->dmamem, 0x0,
sysbus_mmio_get_region(sbd, 0)); sysbus_mmio_get_region(sbd, 0));
ledma = qdev_new(TYPE_SPARC32_LEDMA_DEVICE); ledma = DEVICE(&s->ledma);
object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort); object_property_set_link(OBJECT(ledma), "iommu", iommu, &error_abort);
object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma)); sysbus_realize(SYS_BUS_DEVICE(ledma), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(ledma), &error_fatal);
lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance")); lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));
sbd = SYS_BUS_DEVICE(lance); sbd = SYS_BUS_DEVICE(lance);
@ -421,6 +415,11 @@ static void sparc32_dma_init(Object *obj)
memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE); memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);
sysbus_init_mmio(sbd, &s->dmamem); sysbus_init_mmio(sbd, &s->dmamem);
object_initialize_child(obj, "espdma", &s->espdma,
TYPE_SPARC32_ESPDMA_DEVICE);
object_initialize_child(obj, "ledma", &s->ledma,
TYPE_SPARC32_LEDMA_DEVICE);
} }
static void sparc32_dma_class_init(ObjectClass *klass, void *data) static void sparc32_dma_class_init(ObjectClass *klass, void *data)

28
hw/pci-host/sabre.c
View File

@ -44,7 +44,7 @@
/* /*
* Chipset docs: * Chipset docs:
* PBM: "UltraSPARC IIi User's Manual", * PBM: "UltraSPARC IIi User's Manual",
* http://www.sun.com/processors/manuals/805-0087.pdf * https://web.archive.org/web/20030403110020/http://www.sun.com/processors/manuals/805-0087.pdf
*/ */
#define PBM_PCI_IMR_MASK 0x7fffffff #define PBM_PCI_IMR_MASK 0x7fffffff
@ -120,7 +120,7 @@ static void sabre_config_write(void *opaque, hwaddr addr,
trace_sabre_config_write(addr, val); trace_sabre_config_write(addr, val);
switch (addr & 0xffff) { switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */ case 0x30 ... 0x4f: /* DMA error registers */
/* XXX: not implemented yet */ /* XXX: not implemented yet */
break; break;
@ -195,32 +195,25 @@ static uint64_t sabre_config_read(void *opaque,
hwaddr addr, unsigned size) hwaddr addr, unsigned size)
{ {
SabreState *s = opaque; SabreState *s = opaque;
uint32_t val; uint32_t val = 0;
switch (addr & 0xffff) { switch (addr) {
case 0x30 ... 0x4f: /* DMA error registers */ case 0x30 ... 0x4f: /* DMA error registers */
val = 0;
/* XXX: not implemented yet */ /* XXX: not implemented yet */
break; break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */ case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) { if (addr & 4) {
val = s->pci_irq_map[(addr & 0x3f) >> 3]; val = s->pci_irq_map[(addr & 0x3f) >> 3];
} else {
val = 0;
} }
break; break;
case 0x1000 ... 0x107f: /* OBIO interrupt control */ case 0x1000 ... 0x107f: /* OBIO interrupt control */
if (addr & 4) { if (addr & 4) {
val = s->obio_irq_map[(addr & 0xff) >> 3]; val = s->obio_irq_map[(addr & 0xff) >> 3];
} else {
val = 0;
} }
break; break;
case 0x1080 ... 0x108f: /* PCI bus error */ case 0x1080 ... 0x108f: /* PCI bus error */
if (addr & 4) { if (addr & 4) {
val = s->pci_err_irq_map[(addr & 0xf) >> 3]; val = s->pci_err_irq_map[(addr & 0xf) >> 3];
} else {
val = 0;
} }
break; break;
case 0x2000 ... 0x202f: /* PCI control */ case 0x2000 ... 0x202f: /* PCI control */
@ -229,8 +222,6 @@ static uint64_t sabre_config_read(void *opaque,
case 0xf020 ... 0xf027: /* Reset control */ case 0xf020 ... 0xf027: /* Reset control */
if (addr & 4) { if (addr & 4) {
val = s->reset_control; val = s->reset_control;
} else {
val = 0;
} }
break; break;
case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
@ -239,7 +230,6 @@ static uint64_t sabre_config_read(void *opaque,
case 0xf000 ... 0xf01f: /* FFB config, memory control */ case 0xf000 ... 0xf01f: /* FFB config, memory control */
/* we don't care */ /* we don't care */
default: default:
val = 0;
break; break;
} }
trace_sabre_config_read(addr, val); trace_sabre_config_read(addr, val);
@ -378,16 +368,8 @@ static void sabre_realize(DeviceState *dev, Error **errp)
{ {
SabreState *s = SABRE(dev); SabreState *s = SABRE(dev);
PCIHostState *phb = PCI_HOST_BRIDGE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
PCIDevice *pci_dev; PCIDevice *pci_dev;
/* sabre_config */
sysbus_mmio_map(sbd, 0, s->special_base);
/* PCI configuration space */
sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
/* pci_ioport */
sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
memory_region_add_subregion(get_system_memory(), s->mem_base, memory_region_add_subregion(get_system_memory(), s->mem_base,
&s->pci_mmio); &s->pci_mmio);
@ -396,7 +378,7 @@ static void sabre_realize(DeviceState *dev, Error **errp)
pci_sabre_set_irq, pci_sabre_map_irq, s, pci_sabre_set_irq, pci_sabre_map_irq, s,
&s->pci_mmio, &s->pci_mmio,
&s->pci_ioport, &s->pci_ioport,
0, 32, TYPE_PCI_BUS); 0, 0x40, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);

21
hw/sparc/sun4m.c
View File

@ -319,7 +319,7 @@ static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
static void *sparc32_dma_init(hwaddr dma_base, static void *sparc32_dma_init(hwaddr dma_base,
hwaddr esp_base, qemu_irq espdma_irq, hwaddr esp_base, qemu_irq espdma_irq,
hwaddr le_base, qemu_irq ledma_irq) hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd)
{ {
DeviceState *dma; DeviceState *dma;
ESPDMADeviceState *espdma; ESPDMADeviceState *espdma;
@ -328,16 +328,11 @@ static void *sparc32_dma_init(hwaddr dma_base,
SysBusPCNetState *lance; SysBusPCNetState *lance;
dma = qdev_new(TYPE_SPARC32_DMA); dma = qdev_new(TYPE_SPARC32_DMA);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "espdma")); OBJECT(dma), "espdma"));
sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp")); esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
OBJECT(dma), "ledma")); OBJECT(dma), "ledma"));
@ -345,6 +340,14 @@ static void *sparc32_dma_init(hwaddr dma_base,
lance = SYSBUS_PCNET(object_resolve_path_component( lance = SYSBUS_PCNET(object_resolve_path_component(
OBJECT(ledma), "lance")); OBJECT(ledma), "lance"));
qdev_set_nic_properties(DEVICE(lance), nd);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
return dma; return dma;
@ -850,6 +853,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
unsigned int max_cpus = machine->smp.max_cpus; unsigned int max_cpus = machine->smp.max_cpus;
Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
TYPE_MEMORY_BACKEND, NULL); TYPE_MEMORY_BACKEND, NULL);
NICInfo *nd = &nd_table[0];
if (machine->ram_size > hwdef->max_mem) { if (machine->ram_size > hwdef->max_mem) {
error_report("Too much memory for this machine: %" PRId64 "," error_report("Too much memory for this machine: %" PRId64 ","
@ -910,9 +914,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
hwdef->iommu_pad_base, hwdef->iommu_pad_len); hwdef->iommu_pad_base, hwdef->iommu_pad_len);
} }
qemu_check_nic_model(nd, TYPE_LANCE);
sparc32_dma_init(hwdef->dma_base, sparc32_dma_init(hwdef->dma_base,
hwdef->esp_base, slavio_irq[18], hwdef->esp_base, slavio_irq[18],
hwdef->le_base, slavio_irq[16]); hwdef->le_base, slavio_irq[16], nd);
if (graphic_depth != 8 && graphic_depth != 24) { if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth); error_report("Unsupported depth: %d", graphic_depth);
@ -1049,7 +1054,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
machine->initrd_filename, machine->initrd_filename,
machine->ram_size, &initrd_size); machine->ram_size, &initrd_size);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline,
machine->boot_order, machine->ram_size, kernel_size, machine->boot_order, machine->ram_size, kernel_size,
graphic_width, graphic_height, graphic_depth, graphic_width, graphic_height, graphic_depth,
hwdef->nvram_machine_id, "Sun4m"); hwdef->nvram_machine_id, "Sun4m");

7
hw/sparc64/sun4u.c
View File

@ -588,6 +588,13 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
&error_abort); &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
/* sabre_config */
sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
/* PCI configuration space */
sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
/* pci_ioport */
sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
/* Wire up PCI interrupts to CPU */ /* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) { for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,

8
include/hw/sparc/sparc32_dma.h
View File

@ -28,7 +28,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ESPDMADeviceState, SPARC32_ESPDMA_DEVICE)
struct ESPDMADeviceState { struct ESPDMADeviceState {
DMADeviceState parent_obj; DMADeviceState parent_obj;
SysBusESPState *esp; SysBusESPState esp;
}; };
#define TYPE_SPARC32_LEDMA_DEVICE "sparc32-ledma" #define TYPE_SPARC32_LEDMA_DEVICE "sparc32-ledma"
@ -37,7 +37,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(LEDMADeviceState, SPARC32_LEDMA_DEVICE)
struct LEDMADeviceState { struct LEDMADeviceState {
DMADeviceState parent_obj; DMADeviceState parent_obj;
SysBusPCNetState *lance; SysBusPCNetState lance;
}; };
#define TYPE_SPARC32_DMA "sparc32-dma" #define TYPE_SPARC32_DMA "sparc32-dma"
@ -48,8 +48,8 @@ struct SPARC32DMAState {
MemoryRegion dmamem; MemoryRegion dmamem;
MemoryRegion ledma_alias; MemoryRegion ledma_alias;
ESPDMADeviceState *espdma; ESPDMADeviceState espdma;
LEDMADeviceState *ledma; LEDMADeviceState ledma;
}; };
/* sparc32_dma.c */ /* sparc32_dma.c */