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target/mips/cpu: Calculate the CP0 timer period using the CPU frequency

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The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-10-12 11:57:52 +02:00
parent d225b51220
commit 68b981aa76
1 changed files with 2 additions and 2 deletions
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4
target/mips/cpu.c
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@ -144,13 +144,13 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
*/ */
#define CPU_FREQ_HZ_DEFAULT 200000000 #define CPU_FREQ_HZ_DEFAULT 200000000
#define CP0_COUNT_RATE_DEFAULT 2 #define CP0_COUNT_RATE_DEFAULT 2
#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */
static void mips_cp0_period_set(MIPSCPU *cpu) static void mips_cp0_period_set(MIPSCPU *cpu)
{ {
CPUMIPSState *env = &cpu->env; CPUMIPSState *env = &cpu->env;
env->cp0_count_ns = TIMER_PERIOD_DEFAULT; env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_DEFAULT,
CPU_FREQ_HZ_DEFAULT);
} }
static void mips_cpu_realizefn(DeviceState *dev, Error **errp) static void mips_cpu_realizefn(DeviceState *dev, Error **errp)