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target/arm: Convert UDIV, SDIV to decodetree

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:29:29 -06:00 committed by Peter Maydell
parent 1d7ab0288c
commit 6829837047
2 changed files with 39 additions and 32 deletions
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7
target/arm/tcg/a64.decode
View File

@ -28,6 +28,7 @@
&r rn &r rn
&ri rd imm &ri rd imm
&rri_sf rd rn imm sf &rri_sf rd rn imm sf
&rrr_sf rd rn rm sf
&i imm &i imm
&rr_e rd rn esz &rr_e rd rn esz
&rri_e rd rn imm esz &rri_e rd rn imm esz
@ -652,6 +653,12 @@ CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy
### Data Processing (register) ### Data Processing (register)
# Data Processing (2-source) # Data Processing (2-source)
@rrr_sf sf:1 .......... rm:5 ...... rn:5 rd:5 &rrr_sf
UDIV . 00 11010110 ..... 00001 0 ..... ..... @rrr_sf
SDIV . 00 11010110 ..... 00001 1 ..... ..... @rrr_sf
# Data Processing (1-source) # Data Processing (1-source)
# Logical (shifted reg) # Logical (shifted reg)
# Add/subtract (shifted reg) # Add/subtract (shifted reg)

64
target/arm/tcg/translate-a64.c
View File

@ -7485,6 +7485,36 @@ TRANS(UQRSHRN_si, do_scalar_shift_imm_narrow, a, uqrshrn_fns, 0, false)
TRANS(SQSHRUN_si, do_scalar_shift_imm_narrow, a, sqshrun_fns, MO_SIGN, false) TRANS(SQSHRUN_si, do_scalar_shift_imm_narrow, a, sqshrun_fns, MO_SIGN, false)
TRANS(SQRSHRUN_si, do_scalar_shift_imm_narrow, a, sqrshrun_fns, MO_SIGN, false) TRANS(SQRSHRUN_si, do_scalar_shift_imm_narrow, a, sqrshrun_fns, MO_SIGN, false)
static bool do_div(DisasContext *s, arg_rrr_sf *a, bool is_signed)
{
TCGv_i64 tcg_n, tcg_m, tcg_rd;
tcg_rd = cpu_reg(s, a->rd);
if (!a->sf && is_signed) {
tcg_n = tcg_temp_new_i64();
tcg_m = tcg_temp_new_i64();
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, a->rn));
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, a->rm));
} else {
tcg_n = read_cpu_reg(s, a->rn, a->sf);
tcg_m = read_cpu_reg(s, a->rm, a->sf);
}
if (is_signed) {
gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
} else {
gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
}
if (!a->sf) { /* zero extend final result */
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
return true;
}
TRANS(SDIV, do_div, a, true)
TRANS(UDIV, do_div, a, false)
/* Shift a TCGv src by TCGv shift_amount, put result in dst. /* Shift a TCGv src by TCGv shift_amount, put result in dst.
* Note that it is the caller's responsibility to ensure that the * Note that it is the caller's responsibility to ensure that the
* shift amount is in range (ie 0..31 or 0..63) and provide the ARM * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
@ -8425,32 +8455,6 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
#undef MAP #undef MAP
} }
static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
unsigned int rm, unsigned int rn, unsigned int rd)
{
TCGv_i64 tcg_n, tcg_m, tcg_rd;
tcg_rd = cpu_reg(s, rd);
if (!sf && is_signed) {
tcg_n = tcg_temp_new_i64();
tcg_m = tcg_temp_new_i64();
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
} else {
tcg_n = read_cpu_reg(s, rn, sf);
tcg_m = read_cpu_reg(s, rm, sf);
}
if (is_signed) {
gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
} else {
gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
}
if (!sf) { /* zero extend final result */
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
}
/* LSLV, LSRV, ASRV, RORV */ /* LSLV, LSRV, ASRV, RORV */
static void handle_shift_reg(DisasContext *s, static void handle_shift_reg(DisasContext *s,
@ -8552,12 +8556,6 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
} }
} }
break; break;
case 2: /* UDIV */
handle_div(s, false, sf, rm, rn, rd);
break;
case 3: /* SDIV */
handle_div(s, true, sf, rm, rn, rd);
break;
case 4: /* IRG */ case 4: /* IRG */
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
goto do_unallocated; goto do_unallocated;
@ -8616,6 +8614,8 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
} }
default: default:
do_unallocated: do_unallocated:
case 2: /* UDIV */
case 3: /* SDIV */
unallocated_encoding(s); unallocated_encoding(s);
break; break;
} }