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target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 16:53:28 -07:00
parent 0d1d3aaf64
commit 669e077437
4 changed files with 58 additions and 0 deletions
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4
target/sparc/helper.h
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@ -128,6 +128,10 @@ VIS_CMPHELPER(cmpgt)
VIS_CMPHELPER(cmpeq) VIS_CMPHELPER(cmpeq)
VIS_CMPHELPER(cmple) VIS_CMPHELPER(cmple)
VIS_CMPHELPER(cmpne) VIS_CMPHELPER(cmpne)
DEF_HELPER_FLAGS_2(fcmpeq8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fcmpne8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fcmpule8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fcmpugt8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#endif #endif
#undef VIS_HELPER #undef VIS_HELPER
#undef VIS_CMPHELPER #undef VIS_CMPHELPER

5
target/sparc/insns.decode
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@ -408,6 +408,11 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d
FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d
FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d
FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d
FPCMPEQ8 10 ..... 110110 ..... 1 0010 1010 ..... @r_d_d
FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d
FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r
FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r

9
target/sparc/translate.c
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@ -64,14 +64,18 @@
# define gen_helper_cmask8 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_cmask8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_cmask16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_cmask16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_cmask32 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_cmask32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpeq16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpeq32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpgt16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpgt32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmple16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmple32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpne8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpne16 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fcmpne32 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpule8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fcmpugt8 ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; })
@ -5025,6 +5029,11 @@ TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32)
TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32)
TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32)
TRANS(FPCMPEQ8, VIS3B, do_rdd, a, gen_helper_fcmpeq8)
TRANS(FPCMPNE8, VIS3B, do_rdd, a, gen_helper_fcmpne8)
TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule8)
TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8)
static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
{ {

40
target/sparc/vis_helper.c
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@ -238,6 +238,46 @@ VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
VIS_CMPHELPER(helper_fcmple, FCMPLE) VIS_CMPHELPER(helper_fcmple, FCMPLE)
VIS_CMPHELPER(helper_fcmpne, FCMPNE) VIS_CMPHELPER(helper_fcmpne, FCMPNE)
uint64_t helper_fcmpeq8(uint64_t src1, uint64_t src2)
{
uint64_t a = src1 ^ src2;
uint64_t m = 0x7f7f7f7f7f7f7f7fULL;
uint64_t c = ~(((a & m) + m) | a | m);
/* a.......b.......c.......d.......e.......f.......g.......h....... */
c |= c << 7;
/* ab......bc......cd......de......ef......fg......gh......h....... */
c |= c << 14;
/* abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... */
c |= c << 28;
/* abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... */
return c >> 56;
}
uint64_t helper_fcmpne8(uint64_t src1, uint64_t src2)
{
return helper_fcmpeq8(src1, src2) ^ 0xff;
}
uint64_t helper_fcmpule8(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 8; ++i) {
r |= (s1.VIS_B64(i) <= s2.VIS_B64(i)) << i;
}
return r;
}
uint64_t helper_fcmpugt8(uint64_t src1, uint64_t src2)
{
return helper_fcmpule8(src1, src2) ^ 0xff;
}
uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2) uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2)
{ {
int i; int i;