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target/riscv: Typo fix in sstc() predicate

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We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-11-08 18:26:59 +05:30 committed by Alistair Francis
parent 0a9a6cba8b
commit 6535a44334
1 changed files with 1 additions and 1 deletions
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target/riscv/csr.c
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@ -940,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
} }
if (riscv_cpu_virt_enabled(env)) { if (riscv_cpu_virt_enabled(env)) {
if (!(get_field(env->hcounteren, COUNTEREN_TM) & if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) { get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }