target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
This commit is contained in:
parent
ddc7ef8dfe
commit
6513ca15d8
@ -19,3 +19,6 @@ LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
|
|||||||
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
|
REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3)
|
||||||
|
|
||||||
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
|
REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
|
||||||
|
|
||||||
|
REMOVED 101111 ----- ----- ---------------- # CACHE
|
||||||
|
REMOVED 110011 ----- ----- ---------------- # PREF
|
||||||
|
@ -28619,7 +28619,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
|
|||||||
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
|
gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
|
||||||
break;
|
break;
|
||||||
case OPC_CACHE:
|
case OPC_CACHE:
|
||||||
check_insn_opc_removed(ctx, ISA_MIPS_R6);
|
|
||||||
check_cp0_enabled(ctx);
|
check_cp0_enabled(ctx);
|
||||||
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
|
check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
|
||||||
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
|
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
|
||||||
@ -28628,7 +28627,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
|
|||||||
/* Treat as NOP. */
|
/* Treat as NOP. */
|
||||||
break;
|
break;
|
||||||
case OPC_PREF:
|
case OPC_PREF:
|
||||||
check_insn_opc_removed(ctx, ISA_MIPS_R6);
|
|
||||||
if (ctx->insn_flags & INSN_R5900) {
|
if (ctx->insn_flags & INSN_R5900) {
|
||||||
/* Treat as NOP. */
|
/* Treat as NOP. */
|
||||||
} else {
|
} else {
|
||||||
|
Loading…
x
Reference in New Issue
Block a user