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target/arm: Convert FMLAL, FMLSL to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240524232121.284515-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-24 16:20:49 -07:00 committed by Peter Maydell
parent a9240f482c
commit 641d823142
2 changed files with 51 additions and 103 deletions
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10
target/arm/tcg/a64.decode
View File

@ -797,6 +797,11 @@ FMLA_v 0.00 1110 0.1 ..... 11001 1 ..... ..... @qrrr_sd
FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h FMLS_v 0.00 1110 110 ..... 00001 1 ..... ..... @qrrr_h
FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd FMLS_v 0.00 1110 1.1 ..... 11001 1 ..... ..... @qrrr_sd
FMLAL_v 0.00 1110 001 ..... 11101 1 ..... ..... @qrrr_h
FMLSL_v 0.00 1110 101 ..... 11101 1 ..... ..... @qrrr_h
FMLAL2_v 0.10 1110 001 ..... 11001 1 ..... ..... @qrrr_h
FMLSL2_v 0.10 1110 101 ..... 11001 1 ..... ..... @qrrr_h
FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h FCMEQ_v 0.00 1110 010 ..... 00100 1 ..... ..... @qrrr_h
FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd FCMEQ_v 0.00 1110 0.1 ..... 11100 1 ..... ..... @qrrr_sd
@ -877,3 +882,8 @@ FMLS_vi 0.00 1111 11 0 ..... 0101 . 0 ..... ..... @qrrx_d
FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h FMULX_vi 0.10 1111 00 .. .... 1001 . 0 ..... ..... @qrrx_h
FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s FMULX_vi 0.10 1111 10 . ..... 1001 . 0 ..... ..... @qrrx_s
FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d FMULX_vi 0.10 1111 11 0 ..... 1001 . 0 ..... ..... @qrrx_d
FMLAL_vi 0.00 1111 10 .. .... 0000 . 0 ..... ..... @qrrx_h
FMLSL_vi 0.00 1111 10 .. .... 0100 . 0 ..... ..... @qrrx_h
FMLAL2_vi 0.10 1111 10 .. .... 1000 . 0 ..... ..... @qrrx_h
FMLSL2_vi 0.10 1111 10 .. .... 1100 . 0 ..... ..... @qrrx_h

144
target/arm/tcg/translate-a64.c
View File

@ -5256,6 +5256,24 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnmp[3] = {
}; };
TRANS(FMINNMP_v, do_fp3_vector, a, f_vector_fminnmp) TRANS(FMINNMP_v, do_fp3_vector, a, f_vector_fminnmp)
static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)
{
if (fp_access_check(s)) {
int data = (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm), tcg_env,
a->q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_a64);
}
return true;
}
TRANS_FEAT(FMLAL_v, aa64_fhm, do_fmlal, a, false, false)
TRANS_FEAT(FMLSL_v, aa64_fhm, do_fmlal, a, true, false)
TRANS_FEAT(FMLAL2_v, aa64_fhm, do_fmlal, a, false, true)
TRANS_FEAT(FMLSL2_v, aa64_fhm, do_fmlal, a, true, true)
TRANS(ADDP_v, do_gvec_fn3, a, gen_gvec_addp) TRANS(ADDP_v, do_gvec_fn3, a, gen_gvec_addp)
TRANS(SMAXP_v, do_gvec_fn3_no64, a, gen_gvec_smaxp) TRANS(SMAXP_v, do_gvec_fn3_no64, a, gen_gvec_smaxp)
TRANS(SMINP_v, do_gvec_fn3_no64, a, gen_gvec_sminp) TRANS(SMINP_v, do_gvec_fn3_no64, a, gen_gvec_sminp)
@ -5447,6 +5465,24 @@ static bool do_fmla_vector_idx(DisasContext *s, arg_qrrx_e *a, bool neg)
TRANS(FMLA_vi, do_fmla_vector_idx, a, false) TRANS(FMLA_vi, do_fmla_vector_idx, a, false)
TRANS(FMLS_vi, do_fmla_vector_idx, a, true) TRANS(FMLS_vi, do_fmla_vector_idx, a, true)
static bool do_fmlal_idx(DisasContext *s, arg_qrrx_e *a, bool is_s, bool is_2)
{
if (fp_access_check(s)) {
int data = (a->idx << 2) | (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm), tcg_env,
a->q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_idx_a64);
}
return true;
}
TRANS_FEAT(FMLAL_vi, aa64_fhm, do_fmlal_idx, a, false, false)
TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true, false)
TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true)
TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true)
/* /*
* Advanced SIMD scalar pairwise * Advanced SIMD scalar pairwise
*/ */
@ -10911,78 +10947,6 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
} }
} }
/* Floating point op subgroup of C3.6.16. */
static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
{
/* For floating point ops, the U, size[1] and opcode bits
* together indicate the operation. size[0] indicates single
* or double.
*/
int fpopcode = extract32(insn, 11, 5)
| (extract32(insn, 23, 1) << 5)
| (extract32(insn, 29, 1) << 6);
int is_q = extract32(insn, 30, 1);
int size = extract32(insn, 22, 1);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
if (size == 1 && !is_q) {
unallocated_encoding(s);
return;
}
switch (fpopcode) {
case 0x1d: /* FMLAL */
case 0x3d: /* FMLSL */
case 0x59: /* FMLAL2 */
case 0x79: /* FMLSL2 */
if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
unallocated_encoding(s);
return;
}
if (fp_access_check(s)) {
int is_s = extract32(insn, 23, 1);
int is_2 = extract32(insn, 29, 1);
int data = (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_a64);
}
return;
default:
case 0x18: /* FMAXNM */
case 0x19: /* FMLA */
case 0x1a: /* FADD */
case 0x1b: /* FMULX */
case 0x1c: /* FCMEQ */
case 0x1e: /* FMAX */
case 0x1f: /* FRECPS */
case 0x38: /* FMINNM */
case 0x39: /* FMLS */
case 0x3a: /* FSUB */
case 0x3e: /* FMIN */
case 0x3f: /* FRSQRTS */
case 0x58: /* FMAXNMP */
case 0x5a: /* FADDP */
case 0x5b: /* FMUL */
case 0x5c: /* FCMGE */
case 0x5d: /* FACGE */
case 0x5e: /* FMAXP */
case 0x5f: /* FDIV */
case 0x78: /* FMINNMP */
case 0x7a: /* FABD */
case 0x7d: /* FACGT */
case 0x7c: /* FCMGT */
case 0x7e: /* FMINP */
unallocated_encoding(s);
return;
}
}
/* Integer op subgroup of C3.6.16. */ /* Integer op subgroup of C3.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn) static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{ {
@ -11251,16 +11215,13 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
case 0x3: /* logic ops */ case 0x3: /* logic ops */
disas_simd_3same_logic(s, insn); disas_simd_3same_logic(s, insn);
break; break;
case 0x18 ... 0x31:
/* floating point ops, sz[1] and U are part of opcode */
disas_simd_3same_float(s, insn);
break;
default: default:
disas_simd_3same_int(s, insn); disas_simd_3same_int(s, insn);
break; break;
case 0x14: /* SMAXP, UMAXP */ case 0x14: /* SMAXP, UMAXP */
case 0x15: /* SMINP, UMINP */ case 0x15: /* SMINP, UMINP */
case 0x17: /* ADDP */ case 0x17: /* ADDP */
case 0x18 ... 0x31: /* floating point ops */
unallocated_encoding(s); unallocated_encoding(s);
break; break;
} }
@ -12526,22 +12487,15 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
} }
is_fp = 2; is_fp = 2;
break; break;
case 0x00: /* FMLAL */
case 0x04: /* FMLSL */
case 0x18: /* FMLAL2 */
case 0x1c: /* FMLSL2 */
if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
unallocated_encoding(s);
return;
}
size = MO_16;
/* is_fp, but we pass tcg_env not fp_status. */
break;
default: default:
case 0x00: /* FMLAL */
case 0x01: /* FMLA */ case 0x01: /* FMLA */
case 0x04: /* FMLSL */
case 0x05: /* FMLS */ case 0x05: /* FMLS */
case 0x09: /* FMUL */ case 0x09: /* FMUL */
case 0x18: /* FMLAL2 */
case 0x19: /* FMULX */ case 0x19: /* FMULX */
case 0x1c: /* FMLSL2 */
unallocated_encoding(s); unallocated_encoding(s);
return; return;
} }
@ -12660,22 +12614,6 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
} }
return; return;
case 0x00: /* FMLAL */
case 0x04: /* FMLSL */
case 0x18: /* FMLAL2 */
case 0x1c: /* FMLSL2 */
{
int is_s = extract32(opcode, 2, 1);
int is_2 = u;
int data = (index << 2) | (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), tcg_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_idx_a64);
}
return;
case 0x08: /* MUL */ case 0x08: /* MUL */
if (!is_long && !is_scalar) { if (!is_long && !is_scalar) {
static gen_helper_gvec_3 * const fns[3] = { static gen_helper_gvec_3 * const fns[3] = {