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hw/intc/aspeed: Rename num_ints to num_inpins for clarity

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To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-12-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:20 +08:00 committed by Cédric Le Goater
parent 28194d5d15
commit 63f3618f9b
3 changed files with 24 additions and 20 deletions
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2
hw/arm/aspeed_ast27x0.c
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@ -535,7 +535,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_INTC]); sc->memmap[ASPEED_DEV_INTC]);
/* GICINT orgates -> INTC -> GIC */ /* GICINT orgates -> INTC -> GIC */
for (i = 0; i < ic->num_ints; i++) { for (i = 0; i < ic->num_inpins; i++) {
qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0, qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
qdev_get_gpio_in(DEVICE(&a->intc), i)); qdev_get_gpio_in(DEVICE(&a->intc), i));
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i, sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,

31
hw/intc/aspeed_intc.c
View File

@ -47,8 +47,9 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
const char *name = object_get_typename(OBJECT(s)); const char *name = object_get_typename(OBJECT(s));
if (irq >= aic->num_ints) { if (irq >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid input pin index: %d\n",
__func__, irq); __func__, irq);
return; return;
} }
@ -60,7 +61,7 @@ static void aspeed_intc_update(AspeedINTCState *s, int irq, int level)
/* /*
* The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804. * The address of GICINT128 to GICINT136 are from 0x1000 to 0x1804.
* Utilize "address & 0x0f00" to get the irq and irq output pin index * Utilize "address & 0x0f00" to get the irq and irq output pin index
* The value of irq should be 0 to num_ints. * The value of irq should be 0 to num_inpins.
* The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on. * The irq 0 indicates GICINT128, irq 1 indicates GICINT129 and so on.
*/ */
static void aspeed_intc_set_irq(void *opaque, int irq, int level) static void aspeed_intc_set_irq(void *opaque, int irq, int level)
@ -73,8 +74,8 @@ static void aspeed_intc_set_irq(void *opaque, int irq, int level)
uint32_t enable; uint32_t enable;
int i; int i;
if (irq >= aic->num_ints) { if (irq >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid input pin index: %d\n",
__func__, irq); __func__, irq);
return; return;
} }
@ -134,8 +135,9 @@ static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
irq = (offset & 0x0f00) >> 8; irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) { if (irq >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid input pin index: %d\n",
__func__, irq); __func__, irq);
return; return;
} }
@ -190,8 +192,9 @@ static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
irq = (offset & 0x0f00) >> 8; irq = (offset & 0x0f00) >> 8;
if (irq >= aic->num_ints) { if (irq >= aic->num_inpins) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid interrupt number: %d\n", qemu_log_mask(LOG_GUEST_ERROR,
"%s: Invalid input pin index: %d\n",
__func__, irq); __func__, irq);
return; return;
} }
@ -299,8 +302,8 @@ static void aspeed_intc_instance_init(Object *obj)
AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s); AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
int i; int i;
assert(aic->num_ints <= ASPEED_INTC_NR_INTS); assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS);
for (i = 0; i < aic->num_ints; i++) { for (i = 0; i < aic->num_inpins; i++) {
object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i], object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
TYPE_OR_IRQ); TYPE_OR_IRQ);
object_property_set_int(OBJECT(&s->orgates[i]), "num-lines", object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
@ -338,9 +341,9 @@ static void aspeed_intc_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->iomem_container, aic->reg_offset, memory_region_add_subregion(&s->iomem_container, aic->reg_offset,
&s->iomem); &s->iomem);
qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_ints); qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
for (i = 0; i < aic->num_ints; i++) { for (i = 0; i < aic->num_inpins; i++) {
if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) { if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
return; return;
} }
@ -387,7 +390,7 @@ static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2700 INTC Controller"; dc->desc = "ASPEED 2700 INTC Controller";
aic->num_lines = 32; aic->num_lines = 32;
aic->num_ints = 9; aic->num_inpins = 9;
aic->mem_size = 0x4000; aic->mem_size = 0x4000;
aic->nr_regs = 0x808 >> 2; aic->nr_regs = 0x808 >> 2;
aic->reg_offset = 0x1000; aic->reg_offset = 0x1000;

11
include/hw/intc/aspeed_intc.h
View File

@ -17,6 +17,7 @@
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_INTS 9 #define ASPEED_INTC_NR_INTS 9
#define ASPEED_INTC_MAX_INPINS 9
struct AspeedINTCState { struct AspeedINTCState {
/*< private >*/ /*< private >*/
@ -27,19 +28,19 @@ struct AspeedINTCState {
MemoryRegion iomem_container; MemoryRegion iomem_container;
uint32_t *regs; uint32_t *regs;
OrIRQState orgates[ASPEED_INTC_NR_INTS]; OrIRQState orgates[ASPEED_INTC_MAX_INPINS];
qemu_irq output_pins[ASPEED_INTC_NR_INTS]; qemu_irq output_pins[ASPEED_INTC_NR_INTS];
uint32_t enable[ASPEED_INTC_NR_INTS]; uint32_t enable[ASPEED_INTC_MAX_INPINS];
uint32_t mask[ASPEED_INTC_NR_INTS]; uint32_t mask[ASPEED_INTC_MAX_INPINS];
uint32_t pending[ASPEED_INTC_NR_INTS]; uint32_t pending[ASPEED_INTC_MAX_INPINS];
}; };
struct AspeedINTCClass { struct AspeedINTCClass {
SysBusDeviceClass parent_class; SysBusDeviceClass parent_class;
uint32_t num_lines; uint32_t num_lines;
uint32_t num_ints; uint32_t num_inpins;
uint64_t mem_size; uint64_t mem_size;
uint64_t nr_regs; uint64_t nr_regs;
uint64_t reg_offset; uint64_t reg_offset;