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target/loongarch: Add fixed point shift instruction translation

Browse Source 
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-6-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Song Gao 2022-06-06 20:42:55 +08:00 committed by Richard Henderson
parent 143d6785ef
commit 63cfcd47d7
3 changed files with 129 additions and 0 deletions
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106
target/loongarch/insn_trans/trans_shift.c.inc Normal file
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@ -0,0 +1,106 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shl_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shr_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_sar_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shl_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shr_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_sar_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv_i32 t1 = tcg_temp_new_i32();
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_trunc_tl_i32(t1, src1);
tcg_gen_trunc_tl_i32(t2, t0);
tcg_gen_rotr_i32(t1, t1, t2);
tcg_gen_ext_i32_tl(dest, t1);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
tcg_temp_free(t0);
}
static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_rotr_tl(dest, src1, t0);
tcg_temp_free(t0);
}
static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
gen_set_gpr(a->rd, dest, EXT_NONE);
return true;
}
TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)

22
target/loongarch/insns.decode
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@ -23,6 +23,8 @@
# #
@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
@r_i20 .... ... imm:s20 rd:5 &r_i @r_i20 .... ... imm:s20 rd:5 &r_i
@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
@rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i
@rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
@ -77,3 +79,23 @@ addu16i_d 0001 00 ................ ..... ..... @rr_i16
andi 0000 001101 ............ ..... ..... @rr_ui12 andi 0000 001101 ............ ..... ..... @rr_ui12
ori 0000 001110 ............ ..... ..... @rr_ui12 ori 0000 001110 ............ ..... ..... @rr_ui12
xori 0000 001111 ............ ..... ..... @rr_ui12 xori 0000 001111 ............ ..... ..... @rr_ui12
#
# Fixed point shift operation instruction
#
sll_w 0000 00000001 01110 ..... ..... ..... @rrr
srl_w 0000 00000001 01111 ..... ..... ..... @rrr
sra_w 0000 00000001 10000 ..... ..... ..... @rrr
sll_d 0000 00000001 10001 ..... ..... ..... @rrr
srl_d 0000 00000001 10010 ..... ..... ..... @rrr
sra_d 0000 00000001 10011 ..... ..... ..... @rrr
rotr_w 0000 00000001 10110 ..... ..... ..... @rrr
rotr_d 0000 00000001 10111 ..... ..... ..... @rrr
slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5
slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6
srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5
srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6
srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5
srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6
rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5
rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6

1
target/loongarch/translate.c
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@ -146,6 +146,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "decode-insns.c.inc" #include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{ {