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target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

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Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.

Mechanical change using:

  $ for n in UW UL UQ UO SW SL SQ; do \
      sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
           $(git grep -l MO_TE$n target/microblaze); \
    done

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20241105130431.22564-14-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-09-24 23:17:05 +02:00
parent 2beb871dc2
commit 607854ae7c
1 changed files with 18 additions and 18 deletions
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36
target/microblaze/translate.c
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@ -780,13 +780,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg) static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
} }
static bool trans_lhur(DisasContext *dc, arg_typea *arg) static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
} }
static bool trans_lhuea(DisasContext *dc, arg_typea *arg) static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@ -798,26 +798,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true; return true;
#else #else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif #endif
} }
static bool trans_lhui(DisasContext *dc, arg_typeb *arg) static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{ {
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
} }
static bool trans_lw(DisasContext *dc, arg_typea *arg) static bool trans_lw(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
} }
static bool trans_lwr(DisasContext *dc, arg_typea *arg) static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
} }
static bool trans_lwea(DisasContext *dc, arg_typea *arg) static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@ -829,14 +829,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true; return true;
#else #else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif #endif
} }
static bool trans_lwi(DisasContext *dc, arg_typeb *arg) static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{ {
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
} }
static bool trans_lwx(DisasContext *dc, arg_typea *arg) static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@ -846,7 +846,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */ /* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3); tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr); tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) { if (arg->rd) {
@ -930,13 +930,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg) static bool trans_sh(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
} }
static bool trans_shr(DisasContext *dc, arg_typea *arg) static bool trans_shr(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true); return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
} }
static bool trans_shea(DisasContext *dc, arg_typea *arg) static bool trans_shea(DisasContext *dc, arg_typea *arg)
@ -948,26 +948,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true; return true;
#else #else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif #endif
} }
static bool trans_shi(DisasContext *dc, arg_typeb *arg) static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{ {
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
} }
static bool trans_sw(DisasContext *dc, arg_typea *arg) static bool trans_sw(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
} }
static bool trans_swr(DisasContext *dc, arg_typea *arg) static bool trans_swr(DisasContext *dc, arg_typea *arg)
{ {
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true); return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
} }
static bool trans_swea(DisasContext *dc, arg_typea *arg) static bool trans_swea(DisasContext *dc, arg_typea *arg)
@ -979,14 +979,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true; return true;
#else #else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif #endif
} }
static bool trans_swi(DisasContext *dc, arg_typeb *arg) static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{ {
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm); TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false); return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
} }
static bool trans_swx(DisasContext *dc, arg_typea *arg) static bool trans_swx(DisasContext *dc, arg_typea *arg)
@ -1015,7 +1015,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val, tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd), reg_for_write(dc, arg->rd),
dc->mem_index, MO_TEUL); dc->mem_index, MO_TE | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);