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target/arm: Convert SABA, SABD, UABA, UABD to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:38 -07:00 committed by Peter Maydell
parent 41c34bccc2
commit 5ea1b93ef7
2 changed files with 10 additions and 16 deletions
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4
target/arm/tcg/a64.decode
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@ -922,6 +922,10 @@ SMAX_v 0.00 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e UMAX_v 0.10 1110 ..1 ..... 01100 1 ..... ..... @qrrr_e
SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e SMIN_v 0.00 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e UMIN_v 0.10 1110 ..1 ..... 01101 1 ..... ..... @qrrr_e
SABD_v 0.00 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e
UABD_v 0.10 1110 ..1 ..... 01110 1 ..... ..... @qrrr_e
SABA_v 0.00 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
UABA_v 0.10 1110 ..1 ..... 01111 1 ..... ..... @qrrr_e
### Advanced SIMD scalar x indexed element ### Advanced SIMD scalar x indexed element

22
target/arm/tcg/translate-a64.c
View File

@ -5464,6 +5464,10 @@ TRANS(SMAX_v, do_gvec_fn3_no64, a, tcg_gen_gvec_smax)
TRANS(UMAX_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umax) TRANS(UMAX_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umax)
TRANS(SMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_smin) TRANS(SMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_smin)
TRANS(UMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umin) TRANS(UMIN_v, do_gvec_fn3_no64, a, tcg_gen_gvec_umin)
TRANS(SABA_v, do_gvec_fn3_no64, a, gen_gvec_saba)
TRANS(UABA_v, do_gvec_fn3_no64, a, gen_gvec_uaba)
TRANS(SABD_v, do_gvec_fn3_no64, a, gen_gvec_sabd)
TRANS(UABD_v, do_gvec_fn3_no64, a, gen_gvec_uabd)
static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond) static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond)
{ {
@ -10929,8 +10933,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
return; return;
} }
/* fall through */ /* fall through */
case 0xe: /* SABD, UABD */
case 0xf: /* SABA, UABA */
case 0x12: /* MLA, MLS */ case 0x12: /* MLA, MLS */
if (size == 3) { if (size == 3) {
unallocated_encoding(s); unallocated_encoding(s);
@ -10963,6 +10965,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
case 0x0b: /* SQRSHL, UQRSHL */ case 0x0b: /* SQRSHL, UQRSHL */
case 0x0c: /* SMAX, UMAX */ case 0x0c: /* SMAX, UMAX */
case 0x0d: /* SMIN, UMIN */ case 0x0d: /* SMIN, UMIN */
case 0x0e: /* SABD, UABD */
case 0x0f: /* SABA, UABA */
case 0x10: /* ADD, SUB */ case 0x10: /* ADD, SUB */
case 0x11: /* CMTST, CMEQ */ case 0x11: /* CMTST, CMEQ */
unallocated_encoding(s); unallocated_encoding(s);
@ -10974,20 +10978,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
} }
switch (opcode) { switch (opcode) {
case 0xe: /* SABD, UABD */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size);
}
return;
case 0xf: /* SABA, UABA */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uaba, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_saba, size);
}
return;
case 0x13: /* MUL, PMUL */ case 0x13: /* MUL, PMUL */
if (!u) { /* MUL */ if (!u) { /* MUL */
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);