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i386/cpu: Update cache topology with machine's configuration

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User will configure smp cache topology via -machine smp-cache.

For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://lore.kernel.org/r/20250110145115.1574345-4-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Zhao Liu 2025-01-10 22:51:13 +08:00 committed by Paolo Bonzini
parent 2152b4bfcd
commit 5ca9282d25
1 changed files with 67 additions and 0 deletions
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67
target/i386/cpu.c
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@ -7906,6 +7906,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu)
cpu->hyperv_limits[2] = 0;
}
#ifndef CONFIG_USER_ONLY
static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu,
Error **errp)
{
CPUX86State *env = &cpu->env;
CpuTopologyLevel level;
level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D);
if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
env->cache_info_cpuid4.l1d_cache->share_level = level;
env->cache_info_amd.l1d_cache->share_level = level;
} else {
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D,
env->cache_info_cpuid4.l1d_cache->share_level);
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D,
env->cache_info_amd.l1d_cache->share_level);
}
level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I);
if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
env->cache_info_cpuid4.l1i_cache->share_level = level;
env->cache_info_amd.l1i_cache->share_level = level;
} else {
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I,
env->cache_info_cpuid4.l1i_cache->share_level);
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I,
env->cache_info_amd.l1i_cache->share_level);
}
level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2);
if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
env->cache_info_cpuid4.l2_cache->share_level = level;
env->cache_info_amd.l2_cache->share_level = level;
} else {
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2,
env->cache_info_cpuid4.l2_cache->share_level);
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2,
env->cache_info_amd.l2_cache->share_level);
}
level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3);
if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
env->cache_info_cpuid4.l3_cache->share_level = level;
env->cache_info_amd.l3_cache->share_level = level;
} else {
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3,
env->cache_info_cpuid4.l3_cache->share_level);
machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3,
env->cache_info_amd.l3_cache->share_level);
}
if (!machine_check_smp_cache(ms, errp)) {
return false;
}
return true;
}
#endif
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@ -8145,6 +8203,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
/*
* TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates
* if user didn't set smp_cache.
*/
if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) {
return;
}
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {