target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr
KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() use an 'int ret' variable that is used to do an early 'return' if ret > 0. Both are being called in functions that are also declaring a 'ret' integer, initialized with '0', and this integer is used as return of the function. The result is that the compiler is less than pleased and is pointing shadowing errors: ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_get_regs_csr': ../target/riscv/kvm/kvm-cpu.c:90:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local] 90 | int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:539:5: note: in expansion of macro 'KVM_RISCV_GET_CSR' 539 | KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:536:9: note: shadowed declaration is here 536 | int ret = 0; | ^~~ ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_put_regs_csr': ../target/riscv/kvm/kvm-cpu.c:98:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local] 98 | int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:556:5: note: in expansion of macro 'KVM_RISCV_SET_CSR' 556 | KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:553:9: note: shadowed declaration is here 553 | int ret = 0; | ^~~ The macros are doing early returns for non-zero returns and the local 'ret' variable for both functions is used just to do 'return 0', so remove them from kvm_riscv_get_regs_csr() and kvm_riscv_put_regs_csr() and do a straight 'return 0' in the end. For good measure let's also rename the 'ret' variables in KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() to '_ret' to make them more resilient to these kind of errors. Fixes: 937f0b4512 ("target/riscv: Implement kvm_arch_get_registers") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231123101338.1040134-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -87,17 +87,17 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
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#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \
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do { \
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int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (ret) { \
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return ret; \
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int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (_ret) { \
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return _ret; \
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} \
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} while (0)
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#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
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do { \
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int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (ret) { \
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return ret; \
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int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
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if (_ret) { \
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return _ret; \
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} \
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} while (0)
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@ -533,7 +533,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
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static int kvm_riscv_get_regs_csr(CPUState *cs)
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{
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int ret = 0;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
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@ -545,12 +544,12 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
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KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
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KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
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KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
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return ret;
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return 0;
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}
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static int kvm_riscv_put_regs_csr(CPUState *cs)
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{
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int ret = 0;
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CPURISCVState *env = &RISCV_CPU(cs)->env;
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KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
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@ -563,7 +562,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
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KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
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KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
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return ret;
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return 0;
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}
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static int kvm_riscv_get_regs_fp(CPUState *cs)
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