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target/riscv: log guest errors when reserved bits are set in PTEs

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For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
would silently treat this akin to an unmapped page (as required by the
RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
CVA6) which leads to an apparent QEMU bug.

Instead, log a guest error so that in future, incorrectly set up page
tables can be debugged without bisecting QEMU.

Signed-off-by: julia <midnight@trainwit.ch>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250203061852.2931556-1-midnight@trainwit.ch>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
julia 2025-02-03 17:18:52 +11:00 committed by Alistair Francis
parent bda6522e3f
commit 50df464f8e
1 changed files with 26 additions and 1 deletions
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27
target/riscv/cpu_helper.c
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@ -1472,14 +1472,27 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
ppn = pte >> PTE_PPN_SHIFT;
} else {
if (pte & PTE_RESERVED) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits set in PTE: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}
if (!pbmte && (pte & PTE_PBMT)) {
/* Reserved without Svpbmt. */
qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, "
"and Svpbmt extension is disabled: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}
if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
/* Reserved without Svnapot extension */
qemu_log_mask(LOG_GUEST_ERROR, "%s: N bit set in PTE, "
"and Svnapot extension is disabled: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}
@ -1490,14 +1503,19 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
/* Invalid PTE */
return TRANSLATE_FAIL;
}
if (pte & (PTE_R | PTE_W | PTE_X)) {
goto leaf;
}
/* Inner PTE, continue walking */
if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
/* D, A, and U bits are reserved in non-leaf/inner PTEs */
qemu_log_mask(LOG_GUEST_ERROR, "%s: D, A, or U bits set in non-leaf PTE: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}
/* Inner PTE, continue walking */
base = ppn << PGSHIFT;
}
@ -1507,10 +1525,17 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
leaf:
if (ppn & ((1ULL << ptshift) - 1)) {
/* Misaligned PPN */
qemu_log_mask(LOG_GUEST_ERROR, "%s: PPN bits in PTE is misaligned: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}
if (!pbmte && (pte & PTE_PBMT)) {
/* Reserved without Svpbmt. */
qemu_log_mask(LOG_GUEST_ERROR, "%s: PBMT bits set in PTE, "
"and Svpbmt extension is disabled: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);
return TRANSLATE_FAIL;
}