target/i386: Trivial code motion and code style fix
A new pair of braces has to be added to declare variables in the case block. The code style is also fixed according to the transalte.c itself during the code motion. Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Ziqiao Kong
Richard Henderson
parent
080ac33542
commit
505910a6e2
@ -5919,6 +5919,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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/************************/
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/* floats */
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case 0xd8 ... 0xdf:
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{
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if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
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/* if CR0.EM or CR0.TS are set, generate an FPU exception */
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/* XXX: what to do if illegal op ? */
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@ -5932,7 +5933,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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if (mod != 3) {
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/* memory op */
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gen_lea_modrm(env, s, modrm);
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switch(op) {
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switch (op) {
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case 0x00 ... 0x07: /* fxxxs */
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case 0x10 ... 0x17: /* fixxxl */
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case 0x20 ... 0x27: /* fxxxl */
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@ -5941,7 +5942,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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int op1;
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op1 = op & 7;
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switch(op >> 4) {
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switch (op >> 4) {
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case 0:
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tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
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s->mem_index, MO_LEUL);
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@ -5978,9 +5979,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
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case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
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case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
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switch(op & 7) {
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switch (op & 7) {
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case 0:
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switch(op >> 4) {
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switch (op >> 4) {
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case 0:
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tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
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s->mem_index, MO_LEUL);
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@ -6006,7 +6007,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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break;
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case 1:
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/* XXX: the corresponding CPUID bit must be tested ! */
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switch(op >> 4) {
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switch (op >> 4) {
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case 1:
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gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env);
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tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
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@ -6027,7 +6028,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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default:
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switch(op >> 4) {
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switch (op >> 4) {
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case 0:
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gen_helper_fsts_ST0(s->tmp2_i32, cpu_env);
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tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
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@ -6050,13 +6051,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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s->mem_index, MO_LEUW);
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break;
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}
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if ((op & 7) == 3)
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if ((op & 7) == 3) {
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gen_helper_fpop(cpu_env);
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}
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break;
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}
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break;
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case 0x0c: /* fldenv mem */
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gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1));
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gen_helper_fldenv(cpu_env, s->A0,
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tcg_const_i32(dflag - 1));
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break;
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case 0x0d: /* fldcw mem */
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tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
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@ -6064,7 +6067,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fldcw(cpu_env, s->tmp2_i32);
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break;
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case 0x0e: /* fnstenv mem */
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gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1));
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gen_helper_fstenv(cpu_env, s->A0,
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tcg_const_i32(dflag - 1));
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break;
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case 0x0f: /* fnstcw mem */
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gen_helper_fnstcw(s->tmp2_i32, cpu_env);
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@ -6079,10 +6083,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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case 0x2c: /* frstor mem */
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gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1));
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gen_helper_frstor(cpu_env, s->A0,
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tcg_const_i32(dflag - 1));
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break;
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case 0x2e: /* fnsave mem */
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gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1));
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gen_helper_fsave(cpu_env, s->A0,
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tcg_const_i32(dflag - 1));
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break;
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case 0x2f: /* fnstsw mem */
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gen_helper_fnstsw(s->tmp2_i32, cpu_env);
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@ -6097,12 +6103,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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case 0x3d: /* fildll */
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tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
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tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
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s->mem_index, MO_LEQ);
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gen_helper_fildll_ST0(cpu_env, s->tmp1_i64);
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break;
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case 0x3f: /* fistpll */
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gen_helper_fistll_ST0(s->tmp1_i64, cpu_env);
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ);
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
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s->mem_index, MO_LEQ);
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gen_helper_fpop(cpu_env);
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break;
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default:
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@ -6112,7 +6120,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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/* register float ops */
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opreg = rm;
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switch(op) {
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switch (op) {
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case 0x08: /* fld sti */
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gen_helper_fpush(cpu_env);
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gen_helper_fmov_ST0_STN(cpu_env,
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@ -6124,7 +6132,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
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break;
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case 0x0a: /* grp d9/2 */
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switch(rm) {
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switch (rm) {
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case 0: /* fnop */
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/* check exceptions (FreeBSD FPU probe) */
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gen_helper_fwait(cpu_env);
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@ -6134,7 +6142,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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case 0x0c: /* grp d9/4 */
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switch(rm) {
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switch (rm) {
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case 0: /* fchs */
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gen_helper_fchs_ST0(cpu_env);
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break;
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@ -6154,7 +6162,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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break;
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case 0x0d: /* grp d9/5 */
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{
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switch(rm) {
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switch (rm) {
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case 0:
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gen_helper_fpush(cpu_env);
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gen_helper_fld1_ST0(cpu_env);
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@ -6189,7 +6197,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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case 0x0e: /* grp d9/6 */
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switch(rm) {
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switch (rm) {
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case 0: /* f2xm1 */
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gen_helper_f2xm1(cpu_env);
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break;
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@ -6218,7 +6226,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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case 0x0f: /* grp d9/7 */
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switch(rm) {
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switch (rm) {
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case 0: /* fprem */
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gen_helper_fprem(cpu_env);
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break;
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@ -6255,10 +6263,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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op1 = op & 7;
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if (op >= 0x20) {
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gen_helper_fp_arith_STN_ST0(op1, opreg);
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if (op >= 0x30)
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if (op >= 0x30) {
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gen_helper_fpop(cpu_env);
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}
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} else {
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gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
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gen_helper_fmov_FT0_STN(cpu_env,
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tcg_const_i32(opreg));
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gen_helper_fp_arith_ST0_FT0(op1);
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}
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}
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@ -6276,7 +6286,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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case 0x15: /* da/5 */
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switch(rm) {
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switch (rm) {
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case 1: /* fucompp */
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gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
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gen_helper_fucom_ST0_FT0(cpu_env);
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@ -6288,7 +6298,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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}
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break;
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case 0x1c:
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switch(rm) {
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switch (rm) {
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case 0: /* feni (287 only, just do nop here) */
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break;
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case 1: /* fdisi (287 only, just do nop here) */
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@ -6346,7 +6356,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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case 0x33: /* de/3 */
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switch(rm) {
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switch (rm) {
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case 1: /* fcompp */
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gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
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gen_helper_fcom_ST0_FT0(cpu_env);
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@ -6362,7 +6372,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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gen_helper_fpop(cpu_env);
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break;
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case 0x3c: /* df/4 */
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switch(rm) {
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switch (rm) {
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case 0:
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gen_helper_fnstsw(s->tmp2_i32, cpu_env);
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tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32);
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@ -6418,6 +6428,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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goto unknown_op;
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}
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}
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}
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break;
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/************************/
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/* string ops */
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